src/soc/config/loadstore.py

   1 """ConfigureableLoadStoreUnit and ConfigMemoryPortInterface
   2
   3 allows the type of LoadStoreUnit to be run-time selectable
   4
   5 this allows the same code to be used for both small unit tests
   6 as well as larger ones and so on, without needing large amounts
   7 of unnecessarily-duplicated code
   8 """
   9 from soc.experiment.lsmem import TestMemLoadStoreUnit
  10 from soc.bus.test.test_minerva import TestSRAMBareLoadStoreUnit
  11 from soc.experiment.pi2ls import Pi2LSUI
  12 from soc.experiment.pimem import TestMemoryPortInterface
  13 from soc.minerva.units.loadstore import BareLoadStoreUnit
  14
  15 class ConfigLoadStoreUnit:
  16     def __init__(self, pspec):
  17         lsidict = {'testmem': TestMemLoadStoreUnit,
  18                    'test_bare_wb': TestSRAMBareLoadStoreUnit,
  19                    'bare_wb': BareLoadStoreUnit,
  20                    #'test_cache_wb': TestCacheLoadStoreUnit
  21                   }
  22         lsikls = lsidict[pspec.ldst_ifacetype]
  23         self.lsi = lsikls(pspec)
  24
  25
  26 class ConfigMemoryPortInterface:
  27     def __init__(self, pspec):
  28         self.pspec = pspec
  29         if pspec.ldst_ifacetype == 'testpi':
  30             self.pi = TestMemoryPortInterface(addrwid=pspec.addr_wid, # adr bus
  31                                               regwid=pspec.reg_wid) # data bus
  32             return
  33         self.lsmem = ConfigLoadStoreUnit(pspec)
  34         self.pi = Pi2LSUI("mem", lsui=self.lsmem.lsi,
  35                           addr_wid=pspec.addr_wid, # address range
  36                           mask_wid=pspec.mask_wid, # cache line range
  37                           data_wid=pspec.reg_wid)  # data bus width
  38
  39     def ports(self):
  40         if self.pspec.ldst_ifacetype == 'testpi':
  41             return self.pi.ports()
  42         return list(self.pi.ports()) + self.lsmem.lsi.ports()