src/soc/config/loadstore.py

   1 """ConfigureableLoadStoreUnit and ConfigMemoryPortInterface
   2
   3 allows the type of LoadStoreUnit to be run-time selectable
   4
   5 this allows the same code to be used for both small unit tests
   6 as well as larger ones and so on, without needing large amounts
   7 of unnecessarily-duplicated code
   8 """
   9 from soc.experiment.lsmem import TestMemLoadStoreUnit
  10 from soc.bus.test.test_minerva import TestSRAMBareLoadStoreUnit
  11 from soc.experiment.pi2ls import Pi2LSUI
  12 from soc.experiment.pimem import TestMemoryPortInterface
  13 from soc.minerva.units.loadstore import BareLoadStoreUnit
  14 from soc.fu.mmu.fsm import TestSRAMLoadStore1, LoadStore1 # MMU and DCache
  15
  16 class ConfigLoadStoreUnit:
  17     def __init__(self, pspec):
  18         lsidict = {'testmem': TestMemLoadStoreUnit,
  19                    'test_bare_wb': TestSRAMBareLoadStoreUnit, # SRAM added
  20                    'bare_wb': BareLoadStoreUnit,
  21                    'mmu_cache_wb': LoadStore1,
  22                    'test_mmu_cache_wb': TestSRAMLoadStore1, # SRAM added
  23                   }
  24         lsikls = lsidict[pspec.ldst_ifacetype]
  25         self.lsi = lsikls(pspec)
  26
  27
  28 class ConfigMemoryPortInterface:
  29     def __init__(self, pspec):
  30         self.pspec = pspec
  31         if pspec.ldst_ifacetype == 'testpi':
  32             self.pi = TestMemoryPortInterface(addrwid=pspec.addr_wid, # adr bus
  33                                               regwid=pspec.reg_wid) # data bus
  34             return
  35         self.lsmem = ConfigLoadStoreUnit(pspec)
  36         if self.pspec.ldst_ifacetype in ['mmu_cache_wb', 'test_mmu_cache_wb']:
  37             self.pi = self.lsmem.lsi # LoadStore1 already is a PortInterface
  38             return
  39         self.pi = Pi2LSUI("mem", lsui=self.lsmem.lsi,
  40                           addr_wid=pspec.addr_wid, # address range
  41                           mask_wid=pspec.mask_wid, # cache line range
  42                           data_wid=pspec.reg_wid)  # data bus width
  43
  44     def wb_bus(self):
  45         if self.pspec.ldst_ifacetype in ['mmu_cache_wb', 'test_mmu_cache_wb']:
  46             return self.lsmem.lsi.dbus
  47         return self.lsmem.lsi.slavebus
  48
  49     def ports(self):
  50         if self.pspec.ldst_ifacetype == 'testpi':
  51             return self.pi.ports()
  52         return list(self.pi.ports()) + self.lsmem.lsi.ports()