src/soc/decoder/isa/caller.py

   1 from functools import wraps
   2 from soc.decoder.orderedset import OrderedSet
   3 from soc.decoder.selectable_int import SelectableInt, selectconcat
   4 from collections import namedtuple
   5 import math
   6
   7 instruction_info = namedtuple('instruction_info',
   8                               'func read_regs uninit_regs write_regs op_fields form asmregs')
   9
  10
  11 def create_args(reglist, extra=None):
  12     args = OrderedSet()
  13     for reg in reglist:
  14         args.add(reg)
  15     args = list(args)
  16     if extra:
  17         args = [extra] + args
  18     return args
  19
  20
  21 class Mem:
  22
  23     def __init__(self, bytes_per_word=8):
  24         self.mem = {}
  25         self.bytes_per_word = bytes_per_word
  26         self.word_log2 = math.ceil(math.log2(bytes_per_word))
  27
  28     def _get_shifter_mask(self, width, remainder):
  29         shifter = ((self.bytes_per_word - width) - remainder) * \
  30             8  # bits per byte
  31         mask = (1 << (width * 8)) - 1
  32         return shifter, mask
  33
  34     # TODO: Implement ld/st of lesser width
  35     def ld(self, address, width=8):
  36         remainder = address & (self.bytes_per_word - 1)
  37         address = address >> self.word_log2
  38         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  39         if address in self.mem:
  40             val = self.mem[address]
  41         else:
  42             val = 0
  43
  44         if width != self.bytes_per_word:
  45             shifter, mask = self._get_shifter_mask(width, remainder)
  46             val = val & (mask << shifter)
  47             val >>= shifter
  48         print("Read {:x} from addr {:x}".format(val, address))
  49         return val
  50
  51     def st(self, address, value, width=8):
  52         remainder = address & (self.bytes_per_word - 1)
  53         address = address >> self.word_log2
  54         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  55         print("Writing {:x} to addr {:x}".format(value, address))
  56         if width != self.bytes_per_word:
  57             if address in self.mem:
  58                 val = self.mem[address]
  59             else:
  60                 val = 0
  61             shifter, mask = self._get_shifter_mask(width, remainder)
  62             val &= ~(mask << shifter)
  63             val |= value << shifter
  64             self.mem[address] = val
  65         else:
  66             self.mem[address] = value
  67
  68     def __call__(self, addr, sz):
  69         val = self.ld(addr.value, sz)
  70         print ("memread", addr, sz, val)
  71         return SelectableInt(val, sz*8)
  72
  73     def memassign(self, addr, sz, val):
  74         print ("memassign", addr, sz, val)
  75         self.st(addr.value, val.value, sz)
  76
  77
  78 class GPR(dict):
  79     def __init__(self, decoder, regfile):
  80         dict.__init__(self)
  81         self.sd = decoder
  82         for i in range(32):
  83             self[i] = SelectableInt(regfile[i], 64)
  84
  85     def __call__(self, ridx):
  86         return self[ridx]
  87
  88     def set_form(self, form):
  89         self.form = form
  90
  91     def getz(self, rnum):
  92         #rnum = rnum.value # only SelectableInt allowed
  93         print("GPR getzero", rnum)
  94         if rnum == 0:
  95             return SelectableInt(0, 64)
  96         return self[rnum]
  97
  98     def _get_regnum(self, attr):
  99         getform = self.sd.sigforms[self.form]
 100         rnum = getattr(getform, attr)
 101         return rnum
 102
 103     def ___getitem__(self, attr):
 104         print("GPR getitem", attr)
 105         rnum = self._get_regnum(attr)
 106         return self.regfile[rnum]
 107
 108     def dump(self):
 109         for i in range(0, len(self), 8):
 110             s = []
 111             for j in range(8):
 112                 s.append("%08x" % self[i+j].value)
 113             s = ' '.join(s)
 114             print("reg", "%2d" % i, s)
 115
 116 class PC:
 117     def __init__(self, pc_init=0):
 118         self.CIA = SelectableInt(pc_init, 64)
 119         self.NIA = self.CIA + SelectableInt(4, 64)
 120
 121     def update(self, namespace):
 122         self.CIA = self.NIA
 123         self.NIA = self.CIA + SelectableInt(4, 64)
 124         namespace['CIA'] = self.CIA
 125         namespace['NIA'] = self.NIA
 126
 127
 128 class ISACaller:
 129     # decoder2 - an instance of power_decoder2
 130     # regfile - a list of initial values for the registers
 131     def __init__(self, decoder2, regfile):
 132         self.gpr = GPR(decoder2, regfile)
 133         self.mem = Mem()
 134         self.pc = PC()
 135         self.namespace = {'GPR': self.gpr,
 136                           'MEM': self.mem,
 137                           'memassign': self.memassign,
 138                           'NIA': self.pc.NIA,
 139                           'CIA': self.pc.CIA,
 140                           }
 141
 142         self.decoder = decoder2
 143
 144     def memassign(self, ea, sz, val):
 145         self.mem.memassign(ea, sz, val)
 146
 147     def prep_namespace(self, formname, op_fields):
 148         # TODO: get field names from form in decoder*1* (not decoder2)
 149         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 150         # from spec
 151         # then "yield" fields only from op_fields rather than hard-coded
 152         # list, here.
 153         fields = self.decoder.sigforms[formname]
 154         for name in fields._fields:
 155             if name not in ["RA", "RB", "RT"]:
 156                 sig = getattr(fields, name)
 157                 val = yield sig
 158                 self.namespace[name] = SelectableInt(val, sig.width)
 159
 160     def call(self, name):
 161         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 162         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 163         info = self.instrs[name]
 164         yield from self.prep_namespace(info.form, info.op_fields)
 165
 166         input_names = create_args(info.read_regs | info.uninit_regs)
 167         print(input_names)
 168
 169         inputs = []
 170         for name in input_names:
 171             regnum = yield getattr(self.decoder, name)
 172             regname = "_" + name
 173             self.namespace[regname] = regnum
 174             print('reading reg %d' % regnum)
 175             inputs.append(self.gpr(regnum))
 176         print(inputs)
 177         results = info.func(self, *inputs)
 178         print(results)
 179
 180         if info.write_regs:
 181             output_names = create_args(info.write_regs)
 182             for name, output in zip(output_names, results):
 183                 regnum = yield getattr(self.decoder, name)
 184                 print('writing reg %d' % regnum)
 185                 if output.bits > 64:
 186                     output = SelectableInt(output.value, 64)
 187                 self.gpr[regnum] = output
 188         self.pc.update(self.namespace)
 189
 190
 191 def inject():
 192     """ Decorator factory. """
 193     def variable_injector(func):
 194         @wraps(func)
 195         def decorator(*args, **kwargs):
 196             try:
 197                 func_globals = func.__globals__  # Python 2.6+
 198             except AttributeError:
 199                 func_globals = func.func_globals  # Earlier versions.
 200
 201             context = args[0].namespace
 202             saved_values = func_globals.copy()  # Shallow copy of dict.
 203             func_globals.update(context)
 204
 205             result = func(*args, **kwargs)
 206             #exec (func.__code__, func_globals)
 207
 208             #finally:
 209             #    func_globals = saved_values  # Undo changes.
 210
 211             return result
 212
 213         return decorator
 214
 215     return variable_injector
 216