1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from soc
.regfile
.regfiles
import XERRegs
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from soc
.experiment
.mem_types
import LDSTException
19 from soc
.decoder
.power_regspec_map
import regspec_decode_read
20 from soc
.decoder
.power_regspec_map
import regspec_decode_write
21 from soc
.decoder
.power_decoder
import create_pdecode
22 from soc
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
24 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
25 OutSel
, SPR
, RC
, LDSTMode
,
27 from soc
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
29 from soc
.sv
.svp64
import SVP64Rec
30 from soc
.consts
import MSR
32 from soc
.regfile
.regfiles
import FastRegs
33 from soc
.consts
import TT
34 from soc
.config
.state
import CoreState
35 from soc
.regfile
.util
import spr_to_fast
38 def decode_spr_num(spr
):
39 return Cat(spr
[5:10], spr
[0:5])
42 def instr_is_priv(m
, op
, insn
):
43 """determines if the instruction is privileged or not
46 is_priv_insn
= Signal(reset_less
=True)
48 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
49 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
50 comb
+= is_priv_insn
.eq(1)
52 #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
53 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
54 with m
.If(insn
[20]): # field XFX.spr[-1] i think
55 comb
+= is_priv_insn
.eq(1)
59 class SPRMap(Elaboratable
):
60 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
64 self
.spr_i
= Signal(10, reset_less
=True)
65 self
.spr_o
= Data(SPR
, name
="spr_o")
66 self
.fast_o
= Data(3, name
="fast_o")
68 def elaborate(self
, platform
):
70 with m
.Switch(self
.spr_i
):
71 for i
, x
in enumerate(SPR
):
73 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
74 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
75 for x
, v
in spr_to_fast
.items():
77 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
78 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
82 class SVP64RegExtra(Elaboratable
):
83 """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
85 incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
86 depending on info in one of the positions in the EXTRA field.
88 designed so that "no change" to the 5-bit register number occurs if
89 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
91 see https://libre-soc.org/openpower/sv/svp64/
94 self
.extra
= Signal(10, reset_less
=True)
95 self
.etype
= Signal(SVEtype
, reset_less
=True) # 2 or 3 bits
96 self
.idx
= Signal(SVEXTRA
, reset_less
=True) # which part of extra
97 self
.reg_in
= Signal(5) # incoming reg number (5 bits, RA, RB)
98 self
.reg_out
= Signal(7) # extra-augmented output (7 bits)
99 self
.isvec
= Signal(1) # reg is marked as vector if true
101 def elaborate(self
, platform
):
105 # first get the spec. if not changed it's "scalar identity behaviour"
106 # which is zero which is ok.
109 # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
110 # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
111 # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
112 # the register-extension information. extract those how
113 with m
.Switch(self
.etype
):
114 # 2-bit index selection mode
115 with m
.Case(SVEtype
.EXTRA2
):
116 with m
.Switch(self
.idx
):
117 with m
.Case(SVEXTRA
.Idx0
): # 1st 2 bits
118 comb
+= spec
[1:3].eq(self
.extra
[0:2])
119 with m
.Case(SVEXTRA
.Idx1
): # 2nd 2 bits
120 comb
+= spec
[1:3].eq(self
.extra
[2:4])
121 with m
.Case(SVEXTRA
.Idx2
): # 3rd 2 bits
122 comb
+= spec
[1:3].eq(self
.extra
[4:6])
123 with m
.Case(SVEXTRA
.Idx3
): # 4th 2 bits
124 comb
+= spec
[1:3].eq(self
.extra
[6:8])
125 # 3-bit index selection mode
126 with m
.Case(SVEtype
.EXTRA3
):
127 with m
.Switch(self
.idx
):
128 with m
.Case(SVEXTRA
.Idx0
): # 1st 3 bits
129 comb
+= spec
.eq(self
.extra
[0:3])
130 with m
.Case(SVEXTRA
.Idx1
): # 2nd 3 bits
131 comb
+= spec
.eq(self
.extra
[3:6])
132 with m
.Case(SVEXTRA
.Idx2
): # 3rd 3 bits
133 comb
+= spec
.eq(self
.extra
[6:9])
134 # cannot fit more than 9 bits so there is no 4th thing
136 # now decode it. bit 2 is "scalar/vector". note that spec could be zero
137 # from above, which (by design) has the effect of "no change", below.
139 # simple: isvec is top bit of spec
140 comb
+= self
.isvec
.eq(spec
[2])
142 # decode vector differently from scalar
143 with m
.If(self
.isvec
):
144 # Vector: shifted up, extra in LSBs (RA << 2) | spec[0:1]
145 comb
+= self
.reg_out
.eq(Cat(spec
[:2], self
.reg_in
))
147 # Scalar: not shifted up, extra in MSBs RA | (spec[0:1] << 5)
148 comb
+= self
.reg_out
.eq(Cat(self
.reg_in
, spec
[:2]))
153 class DecodeA(Elaboratable
):
154 """DecodeA from instruction
156 decodes register RA, implicit and explicit CSRs
159 def __init__(self
, dec
):
161 self
.sv_rm
= SVP64Rec() # SVP64 RM field
162 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
163 self
.insn_in
= Signal(32, reset_less
=True)
164 self
.reg_out
= Data(7, name
="reg_a")
165 self
.reg_isvec
= Signal(1, name
="reg_a_isvec") # TODO: in reg_out
166 self
.spr_out
= Data(SPR
, "spr_a")
167 self
.fast_out
= Data(3, "fast_a")
169 def elaborate(self
, platform
):
173 m
.submodules
.sprmap
= sprmap
= SPRMap()
174 m
.submodules
.svdec
= svdec
= SVP64RegExtra()
176 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
177 reg
= Signal(5, reset_less
=True)
179 # select Register A field
180 ra
= Signal(5, reset_less
=True)
181 comb
+= ra
.eq(self
.dec
.RA
)
182 with m
.If((self
.sel_in
== In1Sel
.RA
) |
183 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
184 (ra
!= Const(0, 5)))):
186 comb
+= self
.reg_out
.ok
.eq(1)
188 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
189 # moved it to 1st position (in1_sel)... because
190 rs
= Signal(5, reset_less
=True)
191 comb
+= rs
.eq(self
.dec
.RS
)
192 with m
.If(self
.sel_in
== In1Sel
.RS
):
194 comb
+= self
.reg_out
.ok
.eq(1)
196 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
197 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
198 # which in turn were auto-generated by sv_analysis.py
200 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
201 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
202 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
203 comb
+= svdec
.idx
.eq(op
.sv_in1
) # SVP64 reg #1 (matches in1_sel)
204 comb
+= svdec
.reg_in
.eq(reg
) # 5-bit (RA, RS)
206 # outputs: 7-bit reg number and whether it's vectorised
207 comb
+= self
.reg_out
.data
.eq(svdec
.reg_out
)
208 comb
+= self
.reg_isvec
.eq(svdec
.isvec
)
210 # decode Fast-SPR based on instruction type
211 with m
.Switch(op
.internal_op
):
213 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
214 with m
.Case(MicrOp
.OP_BC
):
215 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
217 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
218 comb
+= self
.fast_out
.ok
.eq(1)
219 with m
.Case(MicrOp
.OP_BCREG
):
220 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
221 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
222 with m
.If(xo9
& ~xo5
):
224 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
225 comb
+= self
.fast_out
.ok
.eq(1)
227 # MFSPR move from SPRs
228 with m
.Case(MicrOp
.OP_MFSPR
):
229 spr
= Signal(10, reset_less
=True)
230 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
231 comb
+= sprmap
.spr_i
.eq(spr
)
232 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
233 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
238 class DecodeAImm(Elaboratable
):
239 """DecodeA immediate from instruction
241 decodes register RA, whether immediate-zero, implicit and
245 def __init__(self
, dec
):
247 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
248 self
.immz_out
= Signal(reset_less
=True)
250 def elaborate(self
, platform
):
254 # zero immediate requested
255 ra
= Signal(5, reset_less
=True)
256 comb
+= ra
.eq(self
.dec
.RA
)
257 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) & (ra
== Const(0, 5))):
258 comb
+= self
.immz_out
.eq(1)
263 class DecodeB(Elaboratable
):
264 """DecodeB from instruction
266 decodes register RB, different forms of immediate (signed, unsigned),
267 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
268 by industry-standard convention, "lane 2" is where fully-decoded
269 immediates are muxed in.
272 def __init__(self
, dec
):
274 self
.sv_rm
= SVP64Rec() # SVP64 RM field
275 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
276 self
.insn_in
= Signal(32, reset_less
=True)
277 self
.reg_out
= Data(7, "reg_b")
278 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
279 self
.fast_out
= Data(3, "fast_b")
281 def elaborate(self
, platform
):
285 m
.submodules
.svdec
= svdec
= SVP64RegExtra()
287 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
288 reg
= Signal(5, reset_less
=True)
290 # select Register B field
291 with m
.Switch(self
.sel_in
):
292 with m
.Case(In2Sel
.RB
):
293 comb
+= reg
.eq(self
.dec
.RB
)
294 comb
+= self
.reg_out
.ok
.eq(1)
295 with m
.Case(In2Sel
.RS
):
296 # for M-Form shiftrot
297 comb
+= reg
.eq(self
.dec
.RS
)
298 comb
+= self
.reg_out
.ok
.eq(1)
300 # now do the SVP64 munging. different from DecodeA only by sv_in2
302 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
303 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
304 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
305 comb
+= svdec
.idx
.eq(op
.sv_in2
) # SVP64 reg #2 (matches in2_sel)
306 comb
+= svdec
.reg_in
.eq(reg
) # 5-bit (RA, RS)
308 # outputs: 7-bit reg number and whether it's vectorised
309 comb
+= self
.reg_out
.data
.eq(svdec
.reg_out
)
310 comb
+= self
.reg_isvec
.eq(svdec
.isvec
)
312 # decode SPR2 based on instruction type
313 # BCREG implicitly uses LR or TAR for 2nd reg
314 # CTR however is already in fast_spr1 *not* 2.
315 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
316 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
317 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
319 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
320 comb
+= self
.fast_out
.ok
.eq(1)
322 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
323 comb
+= self
.fast_out
.ok
.eq(1)
328 class DecodeBImm(Elaboratable
):
329 """DecodeB immediate from instruction
331 def __init__(self
, dec
):
333 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
334 self
.imm_out
= Data(64, "imm_b")
336 def elaborate(self
, platform
):
340 # select Register B Immediate
341 with m
.Switch(self
.sel_in
):
342 with m
.Case(In2Sel
.CONST_UI
): # unsigned
343 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
344 comb
+= self
.imm_out
.ok
.eq(1)
345 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
346 si
= Signal(16, reset_less
=True)
347 comb
+= si
.eq(self
.dec
.SI
)
348 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
349 comb
+= self
.imm_out
.ok
.eq(1)
350 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
351 si_hi
= Signal(32, reset_less
=True)
352 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
353 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
354 comb
+= self
.imm_out
.ok
.eq(1)
355 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
356 ui
= Signal(16, reset_less
=True)
357 comb
+= ui
.eq(self
.dec
.UI
)
358 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
359 comb
+= self
.imm_out
.ok
.eq(1)
360 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
361 li
= Signal(26, reset_less
=True)
362 comb
+= li
.eq(self
.dec
.LI
<< 2)
363 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
364 comb
+= self
.imm_out
.ok
.eq(1)
365 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
366 bd
= Signal(16, reset_less
=True)
367 comb
+= bd
.eq(self
.dec
.BD
<< 2)
368 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
369 comb
+= self
.imm_out
.ok
.eq(1)
370 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
371 ds
= Signal(16, reset_less
=True)
372 comb
+= ds
.eq(self
.dec
.DS
<< 2)
373 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
374 comb
+= self
.imm_out
.ok
.eq(1)
375 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
376 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
377 comb
+= self
.imm_out
.ok
.eq(1)
378 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
379 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
380 comb
+= self
.imm_out
.ok
.eq(1)
381 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
382 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
383 comb
+= self
.imm_out
.ok
.eq(1)
388 class DecodeC(Elaboratable
):
389 """DecodeC from instruction
391 decodes register RC. this is "lane 3" into some CompUnits (not many)
394 def __init__(self
, dec
):
396 self
.sv_rm
= SVP64Rec() # SVP64 RM field
397 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
398 self
.insn_in
= Signal(32, reset_less
=True)
399 self
.reg_out
= Data(7, "reg_c")
400 self
.reg_isvec
= Signal(1, name
="reg_c_isvec") # TODO: in reg_out
402 def elaborate(self
, platform
):
406 m
.submodules
.svdec
= svdec
= SVP64RegExtra()
408 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
409 reg
= Signal(5, reset_less
=True)
411 # select Register C field
412 with m
.Switch(self
.sel_in
):
413 with m
.Case(In3Sel
.RB
):
414 # for M-Form shiftrot
415 comb
+= reg
.eq(self
.dec
.RB
)
416 comb
+= self
.reg_out
.ok
.eq(1)
417 with m
.Case(In3Sel
.RS
):
418 comb
+= reg
.eq(self
.dec
.RS
)
419 comb
+= self
.reg_out
.ok
.eq(1)
421 # now do the SVP64 munging. different from DecodeA only by sv_in3
423 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
424 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
425 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
426 comb
+= svdec
.idx
.eq(op
.sv_in3
) # SVP64 reg #3 (matches in3_sel)
427 comb
+= svdec
.reg_in
.eq(reg
) # 5-bit (RA, RS)
429 # outputs: 7-bit reg number and whether it's vectorised
430 comb
+= self
.reg_out
.data
.eq(svdec
.reg_out
)
431 comb
+= self
.reg_isvec
.eq(svdec
.isvec
)
436 class DecodeOut(Elaboratable
):
437 """DecodeOut from instruction
439 decodes output register RA, RT or SPR
442 def __init__(self
, dec
):
444 self
.sv_rm
= SVP64Rec() # SVP64 RM field
445 self
.sel_in
= Signal(OutSel
, reset_less
=True)
446 self
.insn_in
= Signal(32, reset_less
=True)
447 self
.reg_out
= Data(7, "reg_o")
448 self
.reg_isvec
= Signal(1, name
="reg_o_isvec") # TODO: in reg_out
449 self
.spr_out
= Data(SPR
, "spr_o")
450 self
.fast_out
= Data(3, "fast_o")
452 def elaborate(self
, platform
):
455 m
.submodules
.sprmap
= sprmap
= SPRMap()
457 m
.submodules
.svdec
= svdec
= SVP64RegExtra()
459 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
460 reg
= Signal(5, reset_less
=True)
462 # select Register out field
463 with m
.Switch(self
.sel_in
):
464 with m
.Case(OutSel
.RT
):
465 comb
+= reg
.eq(self
.dec
.RT
)
466 comb
+= self
.reg_out
.ok
.eq(1)
467 with m
.Case(OutSel
.RA
):
468 comb
+= reg
.eq(self
.dec
.RA
)
469 comb
+= self
.reg_out
.ok
.eq(1)
470 with m
.Case(OutSel
.SPR
):
471 spr
= Signal(10, reset_less
=True)
472 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
473 # MFSPR move to SPRs - needs mapping
474 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
475 comb
+= sprmap
.spr_i
.eq(spr
)
476 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
477 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
479 # now do the SVP64 munging. different from DecodeA only by sv_out
481 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
482 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
483 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
484 comb
+= svdec
.idx
.eq(op
.sv_out
) # SVP64 reg out1 (matches out_sel)
485 comb
+= svdec
.reg_in
.eq(reg
) # 5-bit (RA, RS)
487 # outputs: 7-bit reg number and whether it's vectorised
488 comb
+= self
.reg_out
.data
.eq(svdec
.reg_out
)
489 comb
+= self
.reg_isvec
.eq(svdec
.isvec
)
492 with m
.Switch(op
.internal_op
):
494 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
495 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
496 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
498 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
499 comb
+= self
.fast_out
.ok
.eq(1)
501 # RFID 1st spr (fast)
502 with m
.Case(MicrOp
.OP_RFID
):
503 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
504 comb
+= self
.fast_out
.ok
.eq(1)
509 class DecodeOut2(Elaboratable
):
510 """DecodeOut2 from instruction
512 decodes output registers (2nd one). note that RA is *implicit* below,
513 which now causes problems with SVP64
515 TODO: SVP64 is a little more complex, here. svp64 allows extending
516 by one more destination by having one more EXTRA field. RA-as-src
517 is not the same as RA-as-dest. limited in that it's the same first
518 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
519 for operations that have src-as-dest: mostly this is LD/ST-with-update
520 but there are others.
523 def __init__(self
, dec
):
525 self
.sv_rm
= SVP64Rec() # SVP64 RM field
526 self
.sel_in
= Signal(OutSel
, reset_less
=True)
527 self
.lk
= Signal(reset_less
=True)
528 self
.insn_in
= Signal(32, reset_less
=True)
529 self
.reg_out
= Data(7, "reg_o2")
530 #self.reg_isvec = Signal(1, name="reg_o2_isvec") # TODO: in reg_out
531 self
.fast_out
= Data(3, "fast_o2")
533 def elaborate(self
, platform
):
537 #m.submodules.svdec = svdec = SVP64RegExtra()
539 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
540 #reg = Signal(5, reset_less=True)
542 if hasattr(self
.dec
.op
, "upd"):
543 # update mode LD/ST uses read-reg A also as an output
544 with m
.If(self
.dec
.op
.upd
== LDSTMode
.update
):
545 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
546 comb
+= self
.reg_out
.ok
.eq(1)
548 # B, BC or BCREG: potential implicit register (LR) output
549 # these give bl, bcl, bclrl, etc.
550 with m
.Switch(op
.internal_op
):
552 # BC* implicit register (LR)
553 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
554 with m
.If(self
.lk
): # "link" mode
555 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
556 comb
+= self
.fast_out
.ok
.eq(1)
558 # RFID 2nd spr (fast)
559 with m
.Case(MicrOp
.OP_RFID
):
560 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
561 comb
+= self
.fast_out
.ok
.eq(1)
566 class DecodeRC(Elaboratable
):
567 """DecodeRc from instruction
569 decodes Record bit Rc
572 def __init__(self
, dec
):
574 self
.sel_in
= Signal(RC
, reset_less
=True)
575 self
.insn_in
= Signal(32, reset_less
=True)
576 self
.rc_out
= Data(1, "rc")
578 def elaborate(self
, platform
):
582 # select Record bit out field
583 with m
.Switch(self
.sel_in
):
585 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
586 comb
+= self
.rc_out
.ok
.eq(1)
588 comb
+= self
.rc_out
.data
.eq(1)
589 comb
+= self
.rc_out
.ok
.eq(1)
590 with m
.Case(RC
.NONE
):
591 comb
+= self
.rc_out
.data
.eq(0)
592 comb
+= self
.rc_out
.ok
.eq(1)
597 class DecodeOE(Elaboratable
):
598 """DecodeOE from instruction
600 decodes OE field: uses RC decode detection which might not be good
602 -- For now, use "rc" in the decode table to decide whether oe exists.
603 -- This is not entirely correct architecturally: For mulhd and
604 -- mulhdu, the OE field is reserved. It remains to be seen what an
605 -- actual POWER9 does if we set it on those instructions, for now we
606 -- test that further down when assigning to the multiplier oe input.
609 def __init__(self
, dec
):
611 self
.sel_in
= Signal(RC
, reset_less
=True)
612 self
.insn_in
= Signal(32, reset_less
=True)
613 self
.oe_out
= Data(1, "oe")
615 def elaborate(self
, platform
):
620 with m
.Switch(op
.internal_op
):
622 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
624 # XXX ARGH! ignoring OE causes incompatibility with microwatt
625 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
626 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
627 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
628 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
629 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
630 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
634 # all other ops decode OE field
636 # select OE bit out field
637 with m
.Switch(self
.sel_in
):
639 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
640 comb
+= self
.oe_out
.ok
.eq(1)
645 class DecodeCRIn(Elaboratable
):
646 """Decodes input CR from instruction
648 CR indices - insn fields - (not the data *in* the CR) require only 3
649 bits because they refer to CR0-CR7
652 def __init__(self
, dec
):
654 self
.sv_rm
= SVP64Rec() # SVP64 RM field
655 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
656 self
.insn_in
= Signal(32, reset_less
=True)
657 self
.cr_bitfield
= Data(3, "cr_bitfield")
658 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
659 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
660 self
.whole_reg
= Data(8, "cr_fxm")
662 def elaborate(self
, platform
):
664 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
670 comb
+= self
.cr_bitfield
.ok
.eq(0)
671 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
672 comb
+= self
.whole_reg
.ok
.eq(0)
673 with m
.Switch(self
.sel_in
):
674 with m
.Case(CRInSel
.NONE
):
675 pass # No bitfield activated
676 with m
.Case(CRInSel
.CR0
):
677 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
678 comb
+= self
.cr_bitfield
.ok
.eq(1)
679 with m
.Case(CRInSel
.BI
):
680 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
681 comb
+= self
.cr_bitfield
.ok
.eq(1)
682 with m
.Case(CRInSel
.BFA
):
683 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
684 comb
+= self
.cr_bitfield
.ok
.eq(1)
685 with m
.Case(CRInSel
.BA_BB
):
686 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
687 comb
+= self
.cr_bitfield
.ok
.eq(1)
688 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
689 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
690 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
691 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
692 with m
.Case(CRInSel
.BC
):
693 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
694 comb
+= self
.cr_bitfield
.ok
.eq(1)
695 with m
.Case(CRInSel
.WHOLE_REG
):
696 comb
+= self
.whole_reg
.ok
.eq(1)
697 move_one
= Signal(reset_less
=True)
698 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
699 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
700 # must one-hot the FXM field
701 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
702 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
704 # otherwise use all of it
705 comb
+= self
.whole_reg
.data
.eq(0xff)
710 class DecodeCROut(Elaboratable
):
711 """Decodes input CR from instruction
713 CR indices - insn fields - (not the data *in* the CR) require only 3
714 bits because they refer to CR0-CR7
717 def __init__(self
, dec
):
719 self
.sv_rm
= SVP64Rec() # SVP64 RM field
720 self
.rc_in
= Signal(reset_less
=True)
721 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
722 self
.insn_in
= Signal(32, reset_less
=True)
723 self
.cr_bitfield
= Data(3, "cr_bitfield")
724 self
.whole_reg
= Data(8, "cr_fxm")
726 def elaborate(self
, platform
):
730 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
733 comb
+= self
.cr_bitfield
.ok
.eq(0)
734 comb
+= self
.whole_reg
.ok
.eq(0)
735 with m
.Switch(self
.sel_in
):
736 with m
.Case(CROutSel
.NONE
):
737 pass # No bitfield activated
738 with m
.Case(CROutSel
.CR0
):
739 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
740 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
741 with m
.Case(CROutSel
.BF
):
742 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
743 comb
+= self
.cr_bitfield
.ok
.eq(1)
744 with m
.Case(CROutSel
.BT
):
745 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
746 comb
+= self
.cr_bitfield
.ok
.eq(1)
747 with m
.Case(CROutSel
.WHOLE_REG
):
748 comb
+= self
.whole_reg
.ok
.eq(1)
749 move_one
= Signal(reset_less
=True)
750 comb
+= move_one
.eq(self
.insn_in
[20])
751 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
753 # must one-hot the FXM field
754 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
755 with m
.If(ppick
.en_o
):
756 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
758 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
760 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
762 # otherwise use all of it
763 comb
+= self
.whole_reg
.data
.eq(0xff)
767 # dictionary of Input Record field names that, if they exist,
768 # will need a corresponding CSV Decoder file column (actually, PowerOp)
769 # to be decoded (this includes the single bit names)
770 record_names
= {'insn_type': 'internal_op',
771 'fn_unit': 'function_unit',
775 'imm_data': 'in2_sel',
776 'invert_in': 'inv_a',
777 'invert_out': 'inv_out',
780 'output_carry': 'cry_out',
781 'input_carry': 'cry_in',
782 'is_32bit': 'is_32b',
785 'data_len': 'ldst_len',
786 'byte_reverse': 'br',
787 'sign_extend': 'sgn_ext',
792 class PowerDecodeSubset(Elaboratable
):
793 """PowerDecodeSubset: dynamic subset decoder
795 only fields actually requested are copied over. hence, "subset" (duh).
797 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
799 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
802 self
.fn_name
= fn_name
804 opkls
= Decode2ToOperand
805 self
.do
= opkls(fn_name
)
806 col_subset
= self
.get_col_subset(self
.do
)
808 # only needed for "main" PowerDecode2
810 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
)
812 # create decoder if one not already given
814 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
815 row_subset
=self
.rowsubsetfn
)
818 # state information needed by the Decoder
820 state
= CoreState("dec2")
823 def get_col_subset(self
, do
):
824 subset
= {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
825 for k
, v
in record_names
.items():
828 print ("get_col_subset", self
.fn_name
, do
.fields
, subset
)
831 def rowsubsetfn(self
, opcode
, row
):
832 return row
['unit'] == self
.fn_name
835 return self
.dec
.ports() + self
.e
.ports() + self
.sv_rm
.ports()
837 def needs_field(self
, field
, op_field
):
842 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
844 def do_copy(self
, field
, val
, final
=False):
845 if final
or self
.final
:
849 if hasattr(do
, field
) and val
is not None:
850 return getattr(do
, field
).eq(val
)
853 def op_get(self
, op_field
):
854 return getattr(self
.dec
.op
, op_field
, None)
856 def elaborate(self
, platform
):
860 op
, do
= self
.dec
.op
, self
.do
861 msr
, cia
= state
.msr
, state
.pc
863 # fill in for a normal instruction (not an exception)
864 # copy over if non-exception, non-privileged etc. is detected
866 if self
.fn_name
is None:
869 name
= self
.fn_name
+ "tmp"
870 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
)
872 # set up submodule decoders
873 m
.submodules
.dec
= self
.dec
874 m
.submodules
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
875 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
876 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
)
877 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
)
879 # copy instruction through...
881 dec_rc
.insn_in
, dec_oe
.insn_in
,
882 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
]:
883 comb
+= i
.eq(self
.dec
.opcode_in
)
885 # ...and subdecoders' input fields
886 comb
+= dec_rc
.sel_in
.eq(op
.rc_sel
)
887 comb
+= dec_oe
.sel_in
.eq(op
.rc_sel
) # XXX should be OE sel
888 comb
+= self
.dec_cr_in
.sel_in
.eq(op
.cr_in
)
889 comb
+= self
.dec_cr_in
.sv_rm
.eq(self
.sv_rm
)
890 comb
+= self
.dec_cr_out
.sv_rm
.eq(self
.sv_rm
)
891 comb
+= self
.dec_cr_out
.sel_in
.eq(op
.cr_out
)
892 comb
+= self
.dec_cr_out
.rc_in
.eq(dec_rc
.rc_out
.data
)
895 comb
+= self
.do_copy("msr", msr
)
896 comb
+= self
.do_copy("cia", cia
)
898 # set up instruction type
899 # no op: defaults to OP_ILLEGAL
900 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
902 # function unit for decoded instruction: requires minor redirect
904 fn
= self
.op_get("function_unit")
905 spr
= Signal(10, reset_less
=True)
906 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
908 # for first test only forward SPRs 18 and 19 to MMU, when
909 # operation is MTSPR or MFSPR. TODO: add other MMU SPRs
910 with m
.If(((self
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
911 (self
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
)) &
912 ((spr
== SPR
.DSISR
) |
(spr
== SPR
.DAR
))):
913 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
915 comb
+= self
.do_copy("fn_unit",fn
)
918 if self
.needs_field("zero_a", "in1_sel"):
919 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
920 comb
+= dec_ai
.sel_in
.eq(op
.in1_sel
)
921 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
922 if self
.needs_field("imm_data", "in2_sel"):
923 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
924 comb
+= dec_bi
.sel_in
.eq(op
.in2_sel
)
925 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
928 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
929 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
932 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
933 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
934 comb
+= self
.do_copy("write_cr0", self
.dec_cr_out
.cr_bitfield
.ok
)
936 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
937 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
939 # decoded/selected instruction flags
940 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
941 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
942 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
943 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
944 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
945 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
946 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
947 lk
= self
.op_get("lk")
950 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
952 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
953 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
954 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
959 class PowerDecode2(PowerDecodeSubset
):
960 """PowerDecode2: the main instruction decoder.
962 whilst PowerDecode is responsible for decoding the actual opcode, this
963 module encapsulates further specialist, sparse information and
964 expansion of fields that is inconvenient to have in the CSV files.
965 for example: the encoding of the immediates, which are detected
966 and expanded out to their full value from an annotated (enum)
969 implicit register usage is also set up, here. for example: OP_BC
970 requires implicitly reading CTR, OP_RFID requires implicitly writing
973 in addition, PowerDecoder2 is responsible for detecting whether
974 instructions are illegal (or privileged) or not, and instead of
975 just leaving at that, *replacing* the instruction to execute with
976 a suitable alternative (trap).
978 LDSTExceptions are done the cycle _after_ they're detected (after
979 they come out of LDSTCompUnit). basically despite the instruction
980 being decoded, the results of the decode are completely ignored
981 and "exception.happened" used to set the "actual" instruction to
982 "OP_TRAP". the LDSTException data structure gets filled in,
983 in the CompTrapOpSubset and that's what it fills in SRR.
985 to make this work, TestIssuer must notice "exception.happened"
986 after the (failed) LD/ST and copies the LDSTException info from
987 the output, into here (PowerDecoder2). without incrementing PC.
990 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
991 super().__init
__(dec
, opkls
, fn_name
, final
, state
)
992 self
.exc
= LDSTException("dec2_exc")
994 def get_col_subset(self
, opkls
):
995 subset
= super().get_col_subset(opkls
)
996 subset
.add("asmcode")
997 subset
.add("in1_sel")
998 subset
.add("in2_sel")
999 subset
.add("in3_sel")
1000 subset
.add("out_sel")
1001 subset
.add("sv_in1")
1002 subset
.add("sv_in2")
1003 subset
.add("sv_in3")
1004 subset
.add("sv_out")
1005 subset
.add("SV_Etype")
1006 subset
.add("SV_Ptype")
1008 subset
.add("internal_op")
1012 def elaborate(self
, platform
):
1013 m
= super().elaborate(platform
)
1016 e_out
, op
, do_out
= self
.e
, self
.dec
.op
, self
.e
.do
1017 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1021 # fill in for a normal instruction (not an exception)
1022 # copy over if non-exception, non-privileged etc. is detected
1024 # set up submodule decoders
1025 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
1026 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
1027 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
1028 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
1029 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
1031 # copy instruction through...
1032 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1033 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1034 comb
+= i
.eq(self
.dec
.opcode_in
)
1037 for i
in [dec_a
.insn_in
, dec_b
.insn_in
,
1038 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1039 comb
+= i
.eq(self
.sv_rm
)
1041 # ...and subdecoders' input fields
1042 comb
+= dec_a
.sel_in
.eq(op
.in1_sel
)
1043 comb
+= dec_b
.sel_in
.eq(op
.in2_sel
)
1044 comb
+= dec_c
.sel_in
.eq(op
.in3_sel
)
1045 comb
+= dec_o
.sel_in
.eq(op
.out_sel
)
1046 comb
+= dec_o2
.sel_in
.eq(op
.out_sel
)
1047 if hasattr(do
, "lk"):
1048 comb
+= dec_o2
.lk
.eq(do
.lk
)
1050 # registers a, b, c and out and out2 (LD/ST EA)
1051 for to_reg
, fromreg
in (
1052 (e
.read_reg1
, dec_a
.reg_out
),
1053 (e
.read_reg2
, dec_b
.reg_out
),
1054 (e
.read_reg3
, dec_c
.reg_out
),
1055 (e
.write_reg
, dec_o
.reg_out
),
1056 (e
.write_ea
, dec_o2
.reg_out
)):
1057 comb
+= to_reg
.data
.eq(fromreg
.data
)
1058 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1061 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1062 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1065 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1066 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1067 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
)
1068 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
)
1070 # condition registers (CR)
1071 comb
+= e
.read_cr1
.eq(self
.dec_cr_in
.cr_bitfield
)
1072 comb
+= e
.read_cr2
.eq(self
.dec_cr_in
.cr_bitfield_b
)
1073 comb
+= e
.read_cr3
.eq(self
.dec_cr_in
.cr_bitfield_o
)
1074 comb
+= e
.write_cr
.eq(self
.dec_cr_out
.cr_bitfield
)
1076 # sigh this is exactly the sort of thing for which the
1077 # decoder is designed to not need. MTSPR, MFSPR and others need
1078 # access to the XER bits. however setting e.oe is not appropriate
1079 with m
.If(op
.internal_op
== MicrOp
.OP_MFSPR
):
1080 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1081 with m
.If(op
.internal_op
== MicrOp
.OP_CMP
):
1082 comb
+= e
.xer_in
.eq(1<<XERRegs
.SO
) # SO
1083 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
1084 comb
+= e
.xer_out
.eq(1)
1086 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1087 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1088 # *DO NOT* call self.trap here. that would reset absolutely
1089 # everything including destroying read of RA and RB.
1090 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1092 ####################
1093 # ok so the instruction's been decoded, blah blah, however
1094 # now we need to determine if it's actually going to go ahead...
1095 # *or* if in fact it's a privileged operation, whether there's
1096 # an external interrupt, etc. etc. this is a simple priority
1097 # if-elif-elif sequence. decrement takes highest priority,
1098 # EINT next highest, privileged operation third.
1100 # check if instruction is privileged
1101 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1103 # different IRQ conditions
1104 ext_irq_ok
= Signal()
1105 dec_irq_ok
= Signal()
1110 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1111 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1112 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1113 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1115 # LD/ST exceptions. TestIssuer copies the exception info at us
1116 # after a failed LD/ST.
1117 with m
.If(exc
.happened
):
1118 with m
.If(exc
.alignment
):
1119 self
.trap(m
, TT
.PRIV
, 0x600)
1120 with m
.Elif(exc
.instr_fault
):
1121 with m
.If(exc
.segment_fault
):
1122 self
.trap(m
, TT
.PRIV
, 0x480)
1124 # pass exception info to trap to create SRR1
1125 self
.trap(m
, TT
.MEMEXC
, 0x400, exc
)
1127 with m
.If(exc
.segment_fault
):
1128 self
.trap(m
, TT
.PRIV
, 0x380)
1130 self
.trap(m
, TT
.PRIV
, 0x300)
1132 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1133 with m
.Elif(dec_irq_ok
):
1134 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1136 # external interrupt? only if MSR.EE set
1137 with m
.Elif(ext_irq_ok
):
1138 self
.trap(m
, TT
.EINT
, 0x500)
1140 # privileged instruction trap
1141 with m
.Elif(priv_ok
):
1142 self
.trap(m
, TT
.PRIV
, 0x700)
1144 # illegal instruction must redirect to trap. this is done by
1145 # *overwriting* the decoded instruction and starting again.
1146 # (note: the same goes for interrupts and for privileged operations,
1147 # just with different trapaddr and traptype)
1148 with m
.Elif(illeg_ok
):
1149 # illegal instruction trap
1150 self
.trap(m
, TT
.ILLEG
, 0x700)
1152 # no exception, just copy things to the output
1156 ####################
1157 # follow-up after trap/irq to set up SRR0/1
1159 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1160 # Note: OP_SC could actually be modified to just be a trap
1161 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1162 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1163 # TRAP write fast1 = SRR0
1164 comb
+= e_out
.write_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1165 comb
+= e_out
.write_fast1
.ok
.eq(1)
1166 # TRAP write fast2 = SRR1
1167 comb
+= e_out
.write_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1168 comb
+= e_out
.write_fast2
.ok
.eq(1)
1170 # RFID: needs to read SRR0/1
1171 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1172 # TRAP read fast1 = SRR0
1173 comb
+= e_out
.read_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1174 comb
+= e_out
.read_fast1
.ok
.eq(1)
1175 # TRAP read fast2 = SRR1
1176 comb
+= e_out
.read_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1177 comb
+= e_out
.read_fast2
.ok
.eq(1)
1179 # annoying simulator bug
1180 if hasattr(e_out
, "asmcode") and hasattr(self
.dec
.op
, "asmcode"):
1181 comb
+= e_out
.asmcode
.eq(self
.dec
.op
.asmcode
)
1185 def trap(self
, m
, traptype
, trapaddr
, exc
=None):
1186 """trap: this basically "rewrites" the decoded instruction as a trap
1189 op
, e
= self
.dec
.op
, self
.e
1190 comb
+= e
.eq(0) # reset eeeeeverything
1193 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1194 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1195 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1196 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1197 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1198 comb
+= self
.do_copy("ldst_exc", exc
, True) # request type
1199 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # copy of MSR "state"
1200 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1203 def get_rdflags(e
, cu
):
1205 for idx
in range(cu
.n_src
):
1206 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1207 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
1209 print("rdflags", rdl
)
1213 if __name__
== '__main__':
1214 pdecode
= create_pdecode()
1215 dec2
= PowerDecode2(pdecode
)
1216 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1217 with
open("dec2.il", "w") as f
: