1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
12 from nmutil
.iocontrol
import RecordObject
13 from nmutil
.extend
import exts
15 from soc
.decoder
.power_regspec_map
import regspec_decode_read
16 from soc
.decoder
.power_regspec_map
import regspec_decode_write
17 from soc
.decoder
.power_decoder
import create_pdecode
18 from soc
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
20 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
21 OutSel
, SPR
, RC
, LDSTMode
)
22 from soc
.decoder
.decode2execute1
import Decode2ToExecute1Type
, Data
23 from soc
.consts
import MSR
25 from soc
.regfile
.regfiles
import FastRegs
26 from soc
.consts
import TT
27 from soc
.config
.state
import CoreState
30 def decode_spr_num(spr
):
31 return Cat(spr
[5:10], spr
[0:5])
34 def instr_is_priv(m
, op
, insn
):
35 """determines if the instruction is privileged or not
38 is_priv_insn
= Signal(reset_less
=True)
40 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
41 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
42 comb
+= is_priv_insn
.eq(1)
44 #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
45 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
46 with m
.If(insn
[20]): # field XFX.spr[-1] i think
47 comb
+= is_priv_insn
.eq(1)
51 class SPRMap(Elaboratable
):
52 """SPRMap: maps POWER9 SPR numbers to internal enum values
56 self
.spr_i
= Signal(10, reset_less
=True)
57 self
.spr_o
= Signal(SPR
, reset_less
=True)
59 def elaborate(self
, platform
):
61 with m
.Switch(self
.spr_i
):
62 for i
, x
in enumerate(SPR
):
64 m
.d
.comb
+= self
.spr_o
.eq(i
)
68 class DecodeA(Elaboratable
):
69 """DecodeA from instruction
71 decodes register RA, whether immediate-zero, implicit and
75 def __init__(self
, dec
):
77 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
78 self
.insn_in
= Signal(32, reset_less
=True)
79 self
.reg_out
= Data(5, name
="reg_a")
80 self
.immz_out
= Signal(reset_less
=True)
81 self
.spr_out
= Data(SPR
, "spr_a")
82 self
.fast_out
= Data(3, "fast_a")
84 def elaborate(self
, platform
):
87 m
.submodules
.sprmap
= sprmap
= SPRMap()
89 # select Register A field
90 ra
= Signal(5, reset_less
=True)
91 comb
+= ra
.eq(self
.dec
.RA
)
92 with m
.If((self
.sel_in
== In1Sel
.RA
) |
93 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
94 (ra
!= Const(0, 5)))):
95 comb
+= self
.reg_out
.data
.eq(ra
)
96 comb
+= self
.reg_out
.ok
.eq(1)
98 # zero immediate requested
99 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
100 (self
.reg_out
.data
== Const(0, 5))):
101 comb
+= self
.immz_out
.eq(1)
103 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
104 with m
.If(self
.sel_in
== In1Sel
.RS
):
105 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
)
106 comb
+= self
.reg_out
.ok
.eq(1)
108 # decode Fast-SPR based on instruction type
110 with m
.Switch(op
.internal_op
):
112 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
113 with m
.Case(MicrOp
.OP_BC
):
114 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
116 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
117 comb
+= self
.fast_out
.ok
.eq(1)
118 with m
.Case(MicrOp
.OP_BCREG
):
119 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
120 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
121 with m
.If(xo9
& ~xo5
):
123 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
124 comb
+= self
.fast_out
.ok
.eq(1)
126 # MFSPR move from SPRs
127 with m
.Case(MicrOp
.OP_MFSPR
):
128 spr
= Signal(10, reset_less
=True)
129 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
132 with m
.Case(SPR
.CTR
.value
):
133 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
134 comb
+= self
.fast_out
.ok
.eq(1)
135 with m
.Case(SPR
.LR
.value
):
136 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
137 comb
+= self
.fast_out
.ok
.eq(1)
138 with m
.Case(SPR
.TAR
.value
):
139 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
140 comb
+= self
.fast_out
.ok
.eq(1)
141 with m
.Case(SPR
.SRR0
.value
):
142 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
)
143 comb
+= self
.fast_out
.ok
.eq(1)
144 with m
.Case(SPR
.SRR1
.value
):
145 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
)
146 comb
+= self
.fast_out
.ok
.eq(1)
147 with m
.Case(SPR
.XER
.value
):
149 # : map to internal SPR numbers
150 # XXX TODO: dec and tb not to go through mapping.
152 comb
+= sprmap
.spr_i
.eq(spr
)
153 comb
+= self
.spr_out
.data
.eq(sprmap
.spr_o
)
154 comb
+= self
.spr_out
.ok
.eq(1)
159 class DecodeB(Elaboratable
):
160 """DecodeB from instruction
162 decodes register RB, different forms of immediate (signed, unsigned),
163 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
164 by industry-standard convention, "lane 2" is where fully-decoded
165 immediates are muxed in.
168 def __init__(self
, dec
):
170 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
171 self
.insn_in
= Signal(32, reset_less
=True)
172 self
.reg_out
= Data(5, "reg_b")
173 self
.imm_out
= Data(64, "imm_b")
174 self
.fast_out
= Data(3, "fast_b")
176 def elaborate(self
, platform
):
180 # select Register B field
181 with m
.Switch(self
.sel_in
):
182 with m
.Case(In2Sel
.RB
):
183 comb
+= self
.reg_out
.data
.eq(self
.dec
.RB
)
184 comb
+= self
.reg_out
.ok
.eq(1)
185 with m
.Case(In2Sel
.RS
):
186 # for M-Form shiftrot
187 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
)
188 comb
+= self
.reg_out
.ok
.eq(1)
189 with m
.Case(In2Sel
.CONST_UI
): # unsigned
190 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
191 comb
+= self
.imm_out
.ok
.eq(1)
192 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
193 si
= Signal(16, reset_less
=True)
194 comb
+= si
.eq(self
.dec
.SI
)
195 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
196 comb
+= self
.imm_out
.ok
.eq(1)
197 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
198 si_hi
= Signal(32, reset_less
=True)
199 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
200 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
201 comb
+= self
.imm_out
.ok
.eq(1)
202 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
203 ui
= Signal(16, reset_less
=True)
204 comb
+= ui
.eq(self
.dec
.UI
)
205 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
206 comb
+= self
.imm_out
.ok
.eq(1)
207 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
208 li
= Signal(26, reset_less
=True)
209 comb
+= li
.eq(self
.dec
.LI
<< 2)
210 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
211 comb
+= self
.imm_out
.ok
.eq(1)
212 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
213 bd
= Signal(16, reset_less
=True)
214 comb
+= bd
.eq(self
.dec
.BD
<< 2)
215 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
216 comb
+= self
.imm_out
.ok
.eq(1)
217 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
218 ds
= Signal(16, reset_less
=True)
219 comb
+= ds
.eq(self
.dec
.DS
<< 2)
220 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
221 comb
+= self
.imm_out
.ok
.eq(1)
222 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
223 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
224 comb
+= self
.imm_out
.ok
.eq(1)
225 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
226 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
227 comb
+= self
.imm_out
.ok
.eq(1)
228 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
229 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
230 comb
+= self
.imm_out
.ok
.eq(1)
232 # decode SPR2 based on instruction type
234 # BCREG implicitly uses LR or TAR for 2nd reg
235 # CTR however is already in fast_spr1 *not* 2.
236 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
237 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
238 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
240 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
241 comb
+= self
.fast_out
.ok
.eq(1)
243 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
244 comb
+= self
.fast_out
.ok
.eq(1)
249 class DecodeC(Elaboratable
):
250 """DecodeC from instruction
252 decodes register RC. this is "lane 3" into some CompUnits (not many)
255 def __init__(self
, dec
):
257 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
258 self
.insn_in
= Signal(32, reset_less
=True)
259 self
.reg_out
= Data(5, "reg_c")
261 def elaborate(self
, platform
):
265 # select Register C field
266 with m
.Switch(self
.sel_in
):
267 with m
.Case(In3Sel
.RB
):
268 # for M-Form shiftrot
269 comb
+= self
.reg_out
.data
.eq(self
.dec
.RB
)
270 comb
+= self
.reg_out
.ok
.eq(1)
271 with m
.Case(In3Sel
.RS
):
272 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
)
273 comb
+= self
.reg_out
.ok
.eq(1)
278 class DecodeOut(Elaboratable
):
279 """DecodeOut from instruction
281 decodes output register RA, RT or SPR
284 def __init__(self
, dec
):
286 self
.sel_in
= Signal(OutSel
, reset_less
=True)
287 self
.insn_in
= Signal(32, reset_less
=True)
288 self
.reg_out
= Data(5, "reg_o")
289 self
.spr_out
= Data(SPR
, "spr_o")
290 self
.fast_out
= Data(3, "fast_o")
292 def elaborate(self
, platform
):
295 m
.submodules
.sprmap
= sprmap
= SPRMap()
298 # select Register out field
299 with m
.Switch(self
.sel_in
):
300 with m
.Case(OutSel
.RT
):
301 comb
+= self
.reg_out
.data
.eq(self
.dec
.RT
)
302 comb
+= self
.reg_out
.ok
.eq(1)
303 with m
.Case(OutSel
.RA
):
304 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
305 comb
+= self
.reg_out
.ok
.eq(1)
306 with m
.Case(OutSel
.SPR
):
307 spr
= Signal(10, reset_less
=True)
308 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
309 # TODO MTSPR 1st spr (fast)
310 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
313 with m
.Case(SPR
.CTR
.value
):
314 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
315 comb
+= self
.fast_out
.ok
.eq(1)
316 with m
.Case(SPR
.LR
.value
):
317 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
318 comb
+= self
.fast_out
.ok
.eq(1)
319 with m
.Case(SPR
.TAR
.value
):
320 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
321 comb
+= self
.fast_out
.ok
.eq(1)
322 with m
.Case(SPR
.SRR0
.value
):
323 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
)
324 comb
+= self
.fast_out
.ok
.eq(1)
325 with m
.Case(SPR
.SRR1
.value
):
326 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
)
327 comb
+= self
.fast_out
.ok
.eq(1)
328 with m
.Case(SPR
.XER
.value
):
330 # : map to internal SPR numbers
331 # XXX TODO: dec and tb not to go through mapping.
333 comb
+= sprmap
.spr_i
.eq(spr
)
334 comb
+= self
.spr_out
.data
.eq(sprmap
.spr_o
)
335 comb
+= self
.spr_out
.ok
.eq(1)
337 with m
.Switch(op
.internal_op
):
339 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
340 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
341 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
343 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
344 comb
+= self
.fast_out
.ok
.eq(1)
346 # RFID 1st spr (fast)
347 with m
.Case(MicrOp
.OP_RFID
):
348 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
349 comb
+= self
.fast_out
.ok
.eq(1)
354 class DecodeOut2(Elaboratable
):
355 """DecodeOut2 from instruction
357 decodes output registers
360 def __init__(self
, dec
):
362 self
.sel_in
= Signal(OutSel
, reset_less
=True)
363 self
.lk
= Signal(reset_less
=True)
364 self
.insn_in
= Signal(32, reset_less
=True)
365 self
.reg_out
= Data(5, "reg_o")
366 self
.fast_out
= Data(3, "fast_o")
368 def elaborate(self
, platform
):
372 # update mode LD/ST uses read-reg A also as an output
373 with m
.If(self
.dec
.op
.upd
== LDSTMode
.update
):
374 comb
+= self
.reg_out
.eq(self
.dec
.RA
)
375 comb
+= self
.reg_out
.ok
.eq(1)
377 # B, BC or BCREG: potential implicit register (LR) output
378 # these give bl, bcl, bclrl, etc.
380 with m
.Switch(op
.internal_op
):
382 # BC* implicit register (LR)
383 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
384 with m
.If(self
.lk
): # "link" mode
385 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
386 comb
+= self
.fast_out
.ok
.eq(1)
388 # RFID 2nd spr (fast)
389 with m
.Case(MicrOp
.OP_RFID
):
390 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
391 comb
+= self
.fast_out
.ok
.eq(1)
396 class DecodeRC(Elaboratable
):
397 """DecodeRc from instruction
399 decodes Record bit Rc
402 def __init__(self
, dec
):
404 self
.sel_in
= Signal(RC
, reset_less
=True)
405 self
.insn_in
= Signal(32, reset_less
=True)
406 self
.rc_out
= Data(1, "rc")
408 def elaborate(self
, platform
):
412 # select Record bit out field
413 with m
.Switch(self
.sel_in
):
415 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
416 comb
+= self
.rc_out
.ok
.eq(1)
418 comb
+= self
.rc_out
.data
.eq(1)
419 comb
+= self
.rc_out
.ok
.eq(1)
420 with m
.Case(RC
.NONE
):
421 comb
+= self
.rc_out
.data
.eq(0)
422 comb
+= self
.rc_out
.ok
.eq(1)
427 class DecodeOE(Elaboratable
):
428 """DecodeOE from instruction
430 decodes OE field: uses RC decode detection which might not be good
432 -- For now, use "rc" in the decode table to decide whether oe exists.
433 -- This is not entirely correct architecturally: For mulhd and
434 -- mulhdu, the OE field is reserved. It remains to be seen what an
435 -- actual POWER9 does if we set it on those instructions, for now we
436 -- test that further down when assigning to the multiplier oe input.
439 def __init__(self
, dec
):
441 self
.sel_in
= Signal(RC
, reset_less
=True)
442 self
.insn_in
= Signal(32, reset_less
=True)
443 self
.oe_out
= Data(1, "oe")
445 def elaborate(self
, platform
):
450 with m
.Switch(op
.internal_op
):
452 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
453 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
):
456 # all other ops decode OE field
458 # select OE bit out field
459 with m
.Switch(self
.sel_in
):
461 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
462 comb
+= self
.oe_out
.ok
.eq(1)
467 class DecodeCRIn(Elaboratable
):
468 """Decodes input CR from instruction
470 CR indices - insn fields - (not the data *in* the CR) require only 3
471 bits because they refer to CR0-CR7
474 def __init__(self
, dec
):
476 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
477 self
.insn_in
= Signal(32, reset_less
=True)
478 self
.cr_bitfield
= Data(3, "cr_bitfield")
479 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
480 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
481 self
.whole_reg
= Signal(reset_less
=True)
483 def elaborate(self
, platform
):
487 comb
+= self
.cr_bitfield
.ok
.eq(0)
488 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
489 comb
+= self
.whole_reg
.eq(0)
490 with m
.Switch(self
.sel_in
):
491 with m
.Case(CRInSel
.NONE
):
492 pass # No bitfield activated
493 with m
.Case(CRInSel
.CR0
):
494 comb
+= self
.cr_bitfield
.data
.eq(0)
495 comb
+= self
.cr_bitfield
.ok
.eq(1)
496 with m
.Case(CRInSel
.BI
):
497 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
498 comb
+= self
.cr_bitfield
.ok
.eq(1)
499 with m
.Case(CRInSel
.BFA
):
500 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
501 comb
+= self
.cr_bitfield
.ok
.eq(1)
502 with m
.Case(CRInSel
.BA_BB
):
503 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
504 comb
+= self
.cr_bitfield
.ok
.eq(1)
505 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
506 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
507 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
508 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
509 with m
.Case(CRInSel
.BC
):
510 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
511 comb
+= self
.cr_bitfield
.ok
.eq(1)
512 with m
.Case(CRInSel
.WHOLE_REG
):
513 comb
+= self
.whole_reg
.eq(1)
518 class DecodeCROut(Elaboratable
):
519 """Decodes input CR from instruction
521 CR indices - insn fields - (not the data *in* the CR) require only 3
522 bits because they refer to CR0-CR7
525 def __init__(self
, dec
):
527 self
.rc_in
= Signal(reset_less
=True)
528 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
529 self
.insn_in
= Signal(32, reset_less
=True)
530 self
.cr_bitfield
= Data(3, "cr_bitfield")
531 self
.whole_reg
= Signal(reset_less
=True)
533 def elaborate(self
, platform
):
537 comb
+= self
.cr_bitfield
.ok
.eq(0)
538 comb
+= self
.whole_reg
.eq(0)
539 with m
.Switch(self
.sel_in
):
540 with m
.Case(CROutSel
.NONE
):
541 pass # No bitfield activated
542 with m
.Case(CROutSel
.CR0
):
543 comb
+= self
.cr_bitfield
.data
.eq(0)
544 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
545 with m
.Case(CROutSel
.BF
):
546 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
547 comb
+= self
.cr_bitfield
.ok
.eq(1)
548 with m
.Case(CROutSel
.BT
):
549 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
550 comb
+= self
.cr_bitfield
.ok
.eq(1)
551 with m
.Case(CROutSel
.WHOLE_REG
):
552 comb
+= self
.whole_reg
.eq(1)
557 class PowerDecode2(Elaboratable
):
558 """PowerDecode2: the main instruction decoder.
560 whilst PowerDecode is responsible for decoding the actual opcode, this
561 module encapsulates further specialist, sparse information and
562 expansion of fields that is inconvenient to have in the CSV files.
563 for example: the encoding of the immediates, which are detected
564 and expanded out to their full value from an annotated (enum)
567 implicit register usage is also set up, here. for example: OP_BC
568 requires implicitly reading CTR, OP_RFID requires implicitly writing
571 in addition, PowerDecoder2 is responsible for detecting whether
572 instructions are illegal (or privileged) or not, and instead of
573 just leaving at that, *replacing* the instruction to execute with
574 a suitable alternative (trap).
577 def __init__(self
, dec
):
580 self
.e
= Decode2ToExecute1Type()
581 self
.valid
= Signal() # sync signal
583 # state information needed by the Decoder (TODO: this as a Record)
584 self
.state
= CoreState("dec2")
587 return self
.dec
.ports() + self
.e
.ports()
589 def elaborate(self
, platform
):
592 e
, op
, do
= self
.e
, self
.dec
.op
, self
.e
.do
593 msr
, cia
= self
.state
.msr
, self
.state
.pc
595 # set up submodule decoders
596 m
.submodules
.dec
= self
.dec
597 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
598 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
599 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
600 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
601 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
602 m
.submodules
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
603 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
604 m
.submodules
.dec_cr_in
= dec_cr_in
= DecodeCRIn(self
.dec
)
605 m
.submodules
.dec_cr_out
= dec_cr_out
= DecodeCROut(self
.dec
)
607 # copy instruction through...
608 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
609 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
, dec_rc
.insn_in
,
610 dec_oe
.insn_in
, dec_cr_in
.insn_in
, dec_cr_out
.insn_in
]:
611 comb
+= i
.eq(self
.dec
.opcode_in
)
613 # ...and subdecoders' input fields
614 comb
+= dec_a
.sel_in
.eq(op
.in1_sel
)
615 comb
+= dec_b
.sel_in
.eq(op
.in2_sel
)
616 comb
+= dec_c
.sel_in
.eq(op
.in3_sel
)
617 comb
+= dec_o
.sel_in
.eq(op
.out_sel
)
618 comb
+= dec_o2
.sel_in
.eq(op
.out_sel
)
619 comb
+= dec_o2
.lk
.eq(do
.lk
)
620 comb
+= dec_rc
.sel_in
.eq(op
.rc_sel
)
621 comb
+= dec_oe
.sel_in
.eq(op
.rc_sel
) # XXX should be OE sel
622 comb
+= dec_cr_in
.sel_in
.eq(op
.cr_in
)
623 comb
+= dec_cr_out
.sel_in
.eq(op
.cr_out
)
624 comb
+= dec_cr_out
.rc_in
.eq(dec_rc
.rc_out
.data
)
627 comb
+= do
.msr
.eq(msr
)
628 comb
+= do
.cia
.eq(cia
)
630 # set up instruction, pick fn unit
631 # no op: defaults to OP_ILLEGAL
632 comb
+= do
.insn_type
.eq(op
.internal_op
)
633 comb
+= do
.fn_unit
.eq(op
.function_unit
)
635 # registers a, b, c and out and out2 (LD/ST EA)
636 comb
+= e
.read_reg1
.eq(dec_a
.reg_out
)
637 comb
+= e
.read_reg2
.eq(dec_b
.reg_out
)
638 comb
+= e
.read_reg3
.eq(dec_c
.reg_out
)
639 comb
+= e
.write_reg
.eq(dec_o
.reg_out
)
640 comb
+= e
.write_ea
.eq(dec_o2
.reg_out
)
641 comb
+= do
.imm_data
.eq(dec_b
.imm_out
) # immediate in RB (usually)
642 comb
+= do
.zero_a
.eq(dec_a
.immz_out
) # RA==0 detected
645 comb
+= do
.rc
.eq(dec_rc
.rc_out
)
646 comb
+= do
.oe
.eq(dec_oe
.oe_out
)
649 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
650 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
653 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
654 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
655 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
)
656 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
)
658 # condition registers (CR)
659 comb
+= e
.read_cr1
.eq(dec_cr_in
.cr_bitfield
)
660 comb
+= e
.read_cr2
.eq(dec_cr_in
.cr_bitfield_b
)
661 comb
+= e
.read_cr3
.eq(dec_cr_in
.cr_bitfield_o
)
662 comb
+= e
.write_cr
.eq(dec_cr_out
.cr_bitfield
)
664 comb
+= do
.read_cr_whole
.eq(dec_cr_in
.whole_reg
)
665 comb
+= do
.write_cr_whole
.eq(dec_cr_out
.whole_reg
)
666 comb
+= do
.write_cr0
.eq(dec_cr_out
.cr_bitfield
.ok
)
668 # decoded/selected instruction flags
669 comb
+= do
.data_len
.eq(op
.ldst_len
)
670 comb
+= do
.invert_a
.eq(op
.inv_a
)
671 comb
+= do
.invert_out
.eq(op
.inv_out
)
672 comb
+= do
.input_carry
.eq(op
.cry_in
) # carry comes in
673 comb
+= do
.output_carry
.eq(op
.cry_out
) # carry goes out
674 comb
+= do
.is_32bit
.eq(op
.is_32b
)
675 comb
+= do
.is_signed
.eq(op
.sgn
)
677 comb
+= do
.lk
.eq(self
.dec
.LK
) # XXX TODO: accessor
679 comb
+= do
.byte_reverse
.eq(op
.br
)
680 comb
+= do
.sign_extend
.eq(op
.sgn_ext
)
681 comb
+= do
.ldst_mode
.eq(op
.upd
) # LD/ST mode (update, cache-inhibit)
683 # These should be removed eventually
684 comb
+= do
.input_cr
.eq(op
.cr_in
) # condition reg comes in
685 comb
+= do
.output_cr
.eq(op
.cr_out
) # condition reg goes in
687 # sigh this is exactly the sort of thing for which the
688 # decoder is designed to not need. MTSPR, MFSPR and others need
689 # access to the XER bits. however setting e.oe is not appropriate
690 with m
.If(op
.internal_op
== MicrOp
.OP_MFSPR
):
691 comb
+= e
.xer_in
.eq(1)
692 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
693 comb
+= e
.xer_out
.eq(1)
695 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
696 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
697 # *DO NOT* call self.trap here. that would reset absolutely
698 # rverything including destroying read of RA and RB.
699 comb
+= do
.trapaddr
.eq(0x70) # addr=0x700 (strip first nibble)
701 # TODO: get msr, then can do privileged instruction
702 with m
.If(instr_is_priv(m
, op
.internal_op
, e
.do
.insn
) & msr
[MSR
.PR
]):
703 # privileged instruction trap
704 self
.trap(m
, TT
.PRIV
, 0x700)
706 # illegal instruction must redirect to trap. this is done by
707 # *overwriting* the decoded instruction and starting again.
708 # (note: the same goes for interrupts and for privileged operations,
709 # just with different trapaddr and traptype)
710 with m
.Elif(op
.internal_op
== MicrOp
.OP_ILLEGAL
):
711 # illegal instruction trap
712 self
.trap(m
, TT
.ILLEG
, 0x700)
714 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
715 # Note: OP_SC could actually be modified to just be a trap
716 with m
.If((do
.insn_type
== MicrOp
.OP_TRAP
) |
717 (do
.insn_type
== MicrOp
.OP_SC
)):
718 # TRAP write fast1 = SRR0
719 comb
+= e
.write_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
720 comb
+= e
.write_fast1
.ok
.eq(1)
721 # TRAP write fast2 = SRR1
722 comb
+= e
.write_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
723 comb
+= e
.write_fast2
.ok
.eq(1)
725 # RFID: needs to read SRR0/1
726 with m
.If(do
.insn_type
== MicrOp
.OP_RFID
):
727 # TRAP read fast1 = SRR0
728 comb
+= e
.read_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
729 comb
+= e
.read_fast1
.ok
.eq(1)
730 # TRAP read fast2 = SRR1
731 comb
+= e
.read_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
732 comb
+= e
.read_fast2
.ok
.eq(1)
736 def trap(self
, m
, traptype
, trapaddr
):
737 """trap: this basically "rewrites" the decoded instruction as a trap
740 e
, op
, do
= self
.e
, self
.dec
.op
, self
.e
.do
741 comb
+= e
.eq(0) # reset eeeeeverything
743 comb
+= do
.insn
.eq(self
.dec
.opcode_in
)
744 comb
+= do
.insn_type
.eq(MicrOp
.OP_TRAP
)
745 comb
+= do
.fn_unit
.eq(Function
.TRAP
)
746 comb
+= do
.trapaddr
.eq(trapaddr
>> 4) # cut bottom 4 bits
747 comb
+= do
.traptype
.eq(traptype
) # request type
748 comb
+= do
.msr
.eq(self
.state
.msr
) # copy of MSR "state"
749 comb
+= do
.cia
.eq(self
.state
.pc
) # copy of PC "state"
751 def regspecmap_read(self
, regfile
, regname
):
752 """regspecmap_read: provides PowerDecode2 with an encoding relationship
753 to Function Unit port regfiles (read-enable, read regnum, write regnum)
754 regfile and regname arguments are fields 1 and 2 from a given regspec.
756 return regspec_decode_read(self
.e
, regfile
, regname
)
758 def regspecmap_write(self
, regfile
, regname
):
759 """regspecmap_write: provides PowerDecode2 with an encoding relationship
760 to Function Unit port regfiles (write port, write regnum)
761 regfile and regname arguments are fields 1 and 2 from a given regspec.
763 return regspec_decode_write(self
.e
, regfile
, regname
)
765 def rdflags(self
, cu
):
767 for idx
in range(cu
.n_src
):
768 regfile
, regname
, _
= cu
.get_in_spec(idx
)
769 rdflag
, read
= self
.regspecmap_read(regfile
, regname
)
771 print("rdflags", rdl
)
775 if __name__
== '__main__':
776 pdecode
= create_pdecode()
777 dec2
= PowerDecode2(pdecode
)
778 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
779 with
open("dec2.il", "w") as f
: