src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
   7 from nmigen.cli import rtlil
   8
   9 from nmutil.iocontrol import RecordObject
  10 from nmutil.extend import exts
  11
  12 from soc.decoder.power_regspec_map import regspec_decode_read
  13 from soc.decoder.power_regspec_map import regspec_decode_write
  14 from soc.decoder.power_decoder import create_pdecode
  15 from soc.decoder.power_enums import (InternalOp, CryIn, Function,
  16                                      CRInSel, CROutSel,
  17                                      LdstLen, In1Sel, In2Sel, In3Sel,
  18                                      OutSel, SPR, RC)
  19
  20 from soc.regfile.regfiles import FastRegs
  21
  22 # see traptype (and trap main_stage.py)
  23
  24 TT_FP = 1<<0
  25 TT_PRIV = 1<<1
  26 TT_TRAP = 1<<2
  27 TT_ADDR = 1<<3
  28
  29
  30 def instr_is_priv(m, op, insn):
  31     """determines if the instruction is privileged or not
  32     """
  33     comb = m.d.comb
  34     Signal = is_priv_insn(reset_less=True)
  35     with m.Switch(op):
  36         with m.Case(InternalOp.OP_ATTN)  : comb += is_priv_insn.eq(1)
  37         with m.Case(InternalOp.OP_MFMSR) : comb += is_priv_insn.eq(1)
  38         with m.Case(InternalOp.OP_MTMSRD): comb += is_priv_insn.eq(1)
  39         with m.Case(InternalOp.OP_RFID)  : comb += is_priv_insn.eq(1)
  40         with m.Case(InternalOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
  41     with m.If(op == OP_MFSPR | op == OP_MTSPR):
  42         with m.If(insn[20]): # field XFX.spr[-1] i think
  43             comb += is_priv_insn.eq(1)
  44     return is_priv_insn
  45
  46
  47 class DecodeA(Elaboratable):
  48     """DecodeA from instruction
  49
  50     decodes register RA, whether immediate-zero, implicit and
  51     explicit CSRs
  52     """
  53
  54     def __init__(self, dec):
  55         self.dec = dec
  56         self.sel_in = Signal(In1Sel, reset_less=True)
  57         self.insn_in = Signal(32, reset_less=True)
  58         self.reg_out = Data(5, name="reg_a")
  59         self.immz_out = Signal(reset_less=True)
  60         self.spr_out = Data(10, "spr_a")
  61         self.fast_out = Data(3, "fast_a")
  62
  63     def elaborate(self, platform):
  64         m = Module()
  65         comb = m.d.comb
  66
  67         # select Register A field
  68         ra = Signal(5, reset_less=True)
  69         comb += ra.eq(self.dec.RA)
  70         with m.If((self.sel_in == In1Sel.RA) |
  71                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  72                    (ra != Const(0, 5)))):
  73             comb += self.reg_out.data.eq(ra)
  74             comb += self.reg_out.ok.eq(1)
  75
  76         # zero immediate requested
  77         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
  78                   (self.reg_out.data == Const(0, 5))):
  79             comb += self.immz_out.eq(1)
  80
  81         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
  82         with m.If(self.sel_in == In1Sel.RS):
  83             comb += self.reg_out.data.eq(self.dec.RS)
  84             comb += self.reg_out.ok.eq(1)
  85
  86         # decode Fast-SPR based on instruction type
  87         op = self.dec.op
  88         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
  89         with m.If(op.internal_op == InternalOp.OP_BC):
  90             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
  91                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
  92                 comb += self.fast_out.ok.eq(1)
  93         with m.Elif(op.internal_op == InternalOp.OP_BCREG):
  94             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
  95             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
  96             with m.If(xo9 & ~xo5):
  97                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
  98                 comb += self.fast_out.ok.eq(1)
  99
 100         # MFSPR move from SPRs
 101         with m.If(op.internal_op == InternalOp.OP_MFSPR):
 102             # XXX TODO: fast/slow SPR decoding and mapping
 103             comb += self.spr_out.data.eq(self.dec.SPR) # SPR field, XFX
 104             comb += self.spr_out.ok.eq(1)
 105
 106         return m
 107
 108
 109 class Data(Record):
 110
 111     def __init__(self, width, name):
 112         name_ok = "%s_ok" % name
 113         layout = ((name, width), (name_ok, 1))
 114         Record.__init__(self, layout)
 115         self.data = getattr(self, name) # convenience
 116         self.ok = getattr(self, name_ok) # convenience
 117         self.data.reset_less = True # grrr
 118         self.reset_less = True # grrr
 119
 120     def ports(self):
 121         return [self.data, self.ok]
 122
 123
 124 class DecodeB(Elaboratable):
 125     """DecodeB from instruction
 126
 127     decodes register RB, different forms of immediate (signed, unsigned),
 128     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 129     by industry-standard convention, "lane 2" is where fully-decoded
 130     immediates are muxed in.
 131     """
 132
 133     def __init__(self, dec):
 134         self.dec = dec
 135         self.sel_in = Signal(In2Sel, reset_less=True)
 136         self.insn_in = Signal(32, reset_less=True)
 137         self.reg_out = Data(5, "reg_b")
 138         self.imm_out = Data(64, "imm_b")
 139         self.fast_out = Data(3, "fast_b")
 140
 141     def elaborate(self, platform):
 142         m = Module()
 143         comb = m.d.comb
 144
 145         # select Register B field
 146         with m.Switch(self.sel_in):
 147             with m.Case(In2Sel.RB):
 148                 comb += self.reg_out.data.eq(self.dec.RB)
 149                 comb += self.reg_out.ok.eq(1)
 150             with m.Case(In2Sel.RS):
 151                 comb += self.reg_out.data.eq(self.dec.RS) # for M-Form shiftrot
 152                 comb += self.reg_out.ok.eq(1)
 153             with m.Case(In2Sel.CONST_UI):
 154                 comb += self.imm_out.data.eq(self.dec.UI)
 155                 comb += self.imm_out.ok.eq(1)
 156             with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
 157                 comb += self.imm_out.data.eq(
 158                     exts(self.dec.SI, 16, 64))
 159                 comb += self.imm_out.ok.eq(1)
 160             with m.Case(In2Sel.CONST_UI_HI):
 161                 comb += self.imm_out.data.eq(self.dec.UI<<16)
 162                 comb += self.imm_out.ok.eq(1)
 163             with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
 164                 comb += self.imm_out.data.eq(self.dec.SI<<16)
 165                 comb += self.imm_out.data.eq(
 166                     exts(self.dec.SI << 16, 32, 64))
 167                 comb += self.imm_out.ok.eq(1)
 168             with m.Case(In2Sel.CONST_LI):
 169                 comb += self.imm_out.data.eq(self.dec.LI<<2)
 170                 comb += self.imm_out.ok.eq(1)
 171             with m.Case(In2Sel.CONST_BD):
 172                 comb += self.imm_out.data.eq(self.dec.BD<<2)
 173                 comb += self.imm_out.ok.eq(1)
 174             with m.Case(In2Sel.CONST_DS):
 175                 comb += self.imm_out.data.eq(self.dec.DS<<2)
 176                 comb += self.imm_out.ok.eq(1)
 177             with m.Case(In2Sel.CONST_M1):
 178                 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
 179                 comb += self.imm_out.ok.eq(1)
 180             with m.Case(In2Sel.CONST_SH):
 181                 comb += self.imm_out.data.eq(self.dec.sh)
 182                 comb += self.imm_out.ok.eq(1)
 183             with m.Case(In2Sel.CONST_SH32):
 184                 comb += self.imm_out.data.eq(self.dec.SH32)
 185                 comb += self.imm_out.ok.eq(1)
 186
 187         # decode SPR2 based on instruction type
 188         op = self.dec.op
 189         # BCREG implicitly uses LR or TAR for 2nd reg
 190         # CTR however is already in fast_spr1 *not* 2.
 191         with m.If(op.internal_op == InternalOp.OP_BCREG):
 192             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
 193             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
 194             with m.If(~xo9):
 195                 comb += self.fast_out.data.eq(FastRegs.LR)
 196                 comb += self.fast_out.ok.eq(1)
 197             with m.Elif(xo5):
 198                 comb += self.fast_out.data.eq(FastRegs.TAR)
 199                 comb += self.fast_out.ok.eq(1)
 200
 201         return m
 202
 203
 204 class DecodeC(Elaboratable):
 205     """DecodeC from instruction
 206
 207     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 208     """
 209
 210     def __init__(self, dec):
 211         self.dec = dec
 212         self.sel_in = Signal(In3Sel, reset_less=True)
 213         self.insn_in = Signal(32, reset_less=True)
 214         self.reg_out = Data(5, "reg_c")
 215
 216     def elaborate(self, platform):
 217         m = Module()
 218         comb = m.d.comb
 219
 220         # select Register C field
 221         with m.Switch(self.sel_in):
 222             with m.Case(In3Sel.RB):
 223                 comb += self.reg_out.data.eq(self.dec.RB) # for M-Form shiftrot
 224                 comb += self.reg_out.ok.eq(1)
 225             with m.Case(In3Sel.RS):
 226                 comb += self.reg_out.data.eq(self.dec.RS)
 227                 comb += self.reg_out.ok.eq(1)
 228
 229         return m
 230
 231
 232 class DecodeOut(Elaboratable):
 233     """DecodeOut from instruction
 234
 235     decodes output register RA, RT or SPR
 236     """
 237
 238     def __init__(self, dec):
 239         self.dec = dec
 240         self.sel_in = Signal(OutSel, reset_less=True)
 241         self.insn_in = Signal(32, reset_less=True)
 242         self.reg_out = Data(5, "reg_o")
 243         self.spr_out = Data(10, "spr_o")
 244         self.fast_out = Data(3, "fast_o")
 245
 246     def elaborate(self, platform):
 247         m = Module()
 248         comb = m.d.comb
 249         op = self.dec.op
 250
 251         # select Register out field
 252         with m.Switch(self.sel_in):
 253             with m.Case(OutSel.RT):
 254                 comb += self.reg_out.data.eq(self.dec.RT)
 255                 comb += self.reg_out.ok.eq(1)
 256             with m.Case(OutSel.RA):
 257                 comb += self.reg_out.data.eq(self.dec.RA)
 258                 comb += self.reg_out.ok.eq(1)
 259             with m.Case(OutSel.SPR):
 260                 comb += self.spr_out.data.eq(self.dec.SPR) # from XFX
 261                 comb += self.spr_out.ok.eq(1)
 262                 # TODO MTSPR 1st spr (fast)
 263                 with m.If(op.internal_op == InternalOp.OP_MTSPR):
 264                     pass
 265                     """
 266                     sprn := decode_spr_num(f_in.insn);
 267                     v.ispr1 := fast_spr_num(sprn);
 268                     -- Make slow SPRs single issue
 269                     if is_fast_spr(v.ispr1) = '0' then
 270                         v.decode.sgl_pipe := '1';
 271                         -- send MMU-related SPRs to loadstore1
 272                         case sprn is
 273                         when SPR_DAR | SPR_DSISR | SPR_PID | SPR_PRTBL =>
 274                             v.decode.unit := LDST;
 275                         when others =>
 276                         end case;
 277                     end if;
 278                     """
 279
 280
 281         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
 282         op = self.dec.op
 283         with m.If((op.internal_op == InternalOp.OP_BC) |
 284                   (op.internal_op == InternalOp.OP_BCREG)):
 285             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
 286                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
 287                 comb += self.fast_out.ok.eq(1)
 288
 289         # RFID 1st spr (fast)
 290         with m.If(op.internal_op == InternalOp.OP_RFID):
 291             comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
 292             comb += self.fast_out.ok.eq(1)
 293
 294         return m
 295
 296
 297 class DecodeOut2(Elaboratable):
 298     """DecodeOut2 from instruction
 299
 300     decodes output registers
 301     """
 302
 303     def __init__(self, dec):
 304         self.dec = dec
 305         self.sel_in = Signal(OutSel, reset_less=True)
 306         self.lk = Signal(reset_less=True)
 307         self.insn_in = Signal(32, reset_less=True)
 308         self.reg_out = Data(5, "reg_o")
 309         self.fast_out = Data(3, "fast_o")
 310
 311     def elaborate(self, platform):
 312         m = Module()
 313         comb = m.d.comb
 314
 315         # update mode LD/ST uses read-reg A also as an output
 316         with m.If(self.dec.op.upd):
 317             comb += self.reg_out.eq(self.dec.RA)
 318             comb += self.reg_out.ok.eq(1)
 319
 320         # BC or BCREG: potential implicit register (LR) output
 321         op = self.dec.op
 322         with m.If((op.internal_op == InternalOp.OP_BC) |
 323                   (op.internal_op == InternalOp.OP_BCREG)):
 324             with m.If(self.lk): # "link" mode
 325                 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
 326                 comb += self.fast_out.ok.eq(1)
 327
 328         # RFID 2nd spr (fast)
 329         with m.If(op.internal_op == InternalOp.OP_RFID):
 330                 comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
 331                 comb += self.fast_out.ok.eq(1)
 332
 333         return m
 334
 335
 336 class DecodeRC(Elaboratable):
 337     """DecodeRc from instruction
 338
 339     decodes Record bit Rc
 340     """
 341     def __init__(self, dec):
 342         self.dec = dec
 343         self.sel_in = Signal(RC, reset_less=True)
 344         self.insn_in = Signal(32, reset_less=True)
 345         self.rc_out = Data(1, "rc")
 346
 347     def elaborate(self, platform):
 348         m = Module()
 349         comb = m.d.comb
 350
 351         # select Record bit out field
 352         with m.Switch(self.sel_in):
 353             with m.Case(RC.RC):
 354                 comb += self.rc_out.data.eq(self.dec.Rc)
 355                 comb += self.rc_out.ok.eq(1)
 356             with m.Case(RC.ONE):
 357                 comb += self.rc_out.data.eq(1)
 358                 comb += self.rc_out.ok.eq(1)
 359             with m.Case(RC.NONE):
 360                 comb += self.rc_out.data.eq(0)
 361                 comb += self.rc_out.ok.eq(1)
 362
 363         return m
 364
 365
 366 class DecodeOE(Elaboratable):
 367     """DecodeOE from instruction
 368
 369     decodes OE field: uses RC decode detection which might not be good
 370
 371     -- For now, use "rc" in the decode table to decide whether oe exists.
 372     -- This is not entirely correct architecturally: For mulhd and
 373     -- mulhdu, the OE field is reserved. It remains to be seen what an
 374     -- actual POWER9 does if we set it on those instructions, for now we
 375     -- test that further down when assigning to the multiplier oe input.
 376     """
 377     def __init__(self, dec):
 378         self.dec = dec
 379         self.sel_in = Signal(RC, reset_less=True)
 380         self.insn_in = Signal(32, reset_less=True)
 381         self.oe_out = Data(1, "oe")
 382
 383     def elaborate(self, platform):
 384         m = Module()
 385         comb = m.d.comb
 386
 387         # select OE bit out field
 388         with m.Switch(self.sel_in):
 389             with m.Case(RC.RC):
 390                 comb += self.oe_out.data.eq(self.dec.OE)
 391                 comb += self.oe_out.ok.eq(1)
 392
 393         return m
 394
 395 class DecodeCRIn(Elaboratable):
 396     """Decodes input CR from instruction
 397
 398     CR indices - insn fields - (not the data *in* the CR) require only 3
 399     bits because they refer to CR0-CR7
 400     """
 401
 402     def __init__(self, dec):
 403         self.dec = dec
 404         self.sel_in = Signal(CRInSel, reset_less=True)
 405         self.insn_in = Signal(32, reset_less=True)
 406         self.cr_bitfield = Data(3, "cr_bitfield")
 407         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 408         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 409         self.whole_reg = Signal(reset_less=True)
 410
 411     def elaborate(self, platform):
 412         m = Module()
 413         comb = m.d.comb
 414
 415         comb += self.cr_bitfield.ok.eq(0)
 416         comb += self.cr_bitfield_b.ok.eq(0)
 417         comb += self.whole_reg.eq(0)
 418         with m.Switch(self.sel_in):
 419             with m.Case(CRInSel.NONE):
 420                 pass # No bitfield activated
 421             with m.Case(CRInSel.CR0):
 422                 comb += self.cr_bitfield.data.eq(0)
 423                 comb += self.cr_bitfield.ok.eq(1)
 424             with m.Case(CRInSel.BI):
 425                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 426                 comb += self.cr_bitfield.ok.eq(1)
 427             with m.Case(CRInSel.BFA):
 428                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 429                 comb += self.cr_bitfield.ok.eq(1)
 430             with m.Case(CRInSel.BA_BB):
 431                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 432                 comb += self.cr_bitfield.ok.eq(1)
 433                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 434                 comb += self.cr_bitfield_b.ok.eq(1)
 435                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 436                 comb += self.cr_bitfield_o.ok.eq(1)
 437             with m.Case(CRInSel.BC):
 438                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 439                 comb += self.cr_bitfield.ok.eq(1)
 440             with m.Case(CRInSel.WHOLE_REG):
 441                 comb += self.whole_reg.eq(1)
 442
 443         return m
 444
 445
 446 class DecodeCROut(Elaboratable):
 447     """Decodes input CR from instruction
 448
 449     CR indices - insn fields - (not the data *in* the CR) require only 3
 450     bits because they refer to CR0-CR7
 451     """
 452
 453     def __init__(self, dec):
 454         self.dec = dec
 455         self.rc_in = Signal(reset_less=True)
 456         self.sel_in = Signal(CROutSel, reset_less=True)
 457         self.insn_in = Signal(32, reset_less=True)
 458         self.cr_bitfield = Data(3, "cr_bitfield")
 459         self.whole_reg = Signal(reset_less=True)
 460
 461     def elaborate(self, platform):
 462         m = Module()
 463         comb = m.d.comb
 464
 465         comb += self.cr_bitfield.ok.eq(0)
 466         comb += self.whole_reg.eq(0)
 467         with m.Switch(self.sel_in):
 468             with m.Case(CROutSel.NONE):
 469                 pass # No bitfield activated
 470             with m.Case(CROutSel.CR0):
 471                 comb += self.cr_bitfield.data.eq(0)
 472                 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
 473             with m.Case(CROutSel.BF):
 474                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
 475                 comb += self.cr_bitfield.ok.eq(1)
 476             with m.Case(CROutSel.BT):
 477                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 478                 comb += self.cr_bitfield.ok.eq(1)
 479             with m.Case(CROutSel.WHOLE_REG):
 480                 comb += self.whole_reg.eq(1)
 481
 482         return m
 483
 484
 485 class XerBits:
 486     def __init__(self):
 487         self.ca = Signal(2, reset_less=True)
 488         self.ov = Signal(2, reset_less=True)
 489         self.so = Signal(reset_less=True)
 490
 491     def ports(self):
 492         return [self.ca, self.ov, self.so]
 493
 494
 495 class Decode2ToExecute1Type(RecordObject):
 496
 497     def __init__(self, name=None):
 498
 499         RecordObject.__init__(self, name=name)
 500
 501         self.valid = Signal(reset_less=True)
 502         self.insn_type = Signal(InternalOp, reset_less=True)
 503         self.fn_unit = Signal(Function, reset_less=True)
 504         self.nia = Signal(64, reset_less=True)
 505         self.write_reg = Data(5, name="rego")
 506         self.write_ea = Data(5, name="ea") # for LD/ST in update mode
 507         self.read_reg1 = Data(5, name="reg1")
 508         self.read_reg2 = Data(5, name="reg2")
 509         self.read_reg3 = Data(5, name="reg3")
 510         self.imm_data = Data(64, name="imm")
 511         self.write_spr = Data(10, name="spro")
 512         self.read_spr1 = Data(10, name="spr1")
 513         self.read_spr2 = Data(10, name="spr2")
 514
 515         self.read_fast1 = Data(3, name="fast1")
 516         self.read_fast2 = Data(3, name="fast2")
 517         self.write_fast1 = Data(3, name="fasto1")
 518         self.write_fast2 = Data(3, name="fasto2")
 519
 520         self.read_cr1 = Data(3, name="cr_in1")
 521         self.read_cr2 = Data(3, name="cr_in2")
 522         self.read_cr3 = Data(3, name="cr_in2")
 523         self.read_cr_whole = Signal(reset_less=True)
 524         self.write_cr = Data(3, name="cr_out")
 525         self.write_cr_whole = Signal(reset_less=True)
 526         self.lk = Signal(reset_less=True)
 527         self.rc = Data(1, "rc")
 528         self.oe = Data(1, "oe")
 529         self.invert_a = Signal(reset_less=True)
 530         self.zero_a = Signal(reset_less=True)
 531         self.invert_out = Signal(reset_less=True)
 532         self.input_carry = Signal(CryIn, reset_less=True)
 533         self.output_carry = Signal(reset_less=True)
 534         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
 535         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
 536         self.is_32bit = Signal(reset_less=True)
 537         self.is_signed = Signal(reset_less=True)
 538         self.insn = Signal(32, reset_less=True)
 539         self.data_len = Signal(4, reset_less=True) # bytes
 540         self.byte_reverse  = Signal(reset_less=True)
 541         self.sign_extend  = Signal(reset_less=True)# do we need this?
 542         self.update  = Signal(reset_less=True) # LD/ST is "update" variant
 543         self.traptype  = Signal(4, reset_less=True) # see trap main_stage.py
 544         self.trapaddr  = Signal(13, reset_less=True)
 545
 546
 547 class PowerDecode2(Elaboratable):
 548
 549     def __init__(self, dec):
 550
 551         self.dec = dec
 552         self.e = Decode2ToExecute1Type()
 553
 554     def ports(self):
 555         return self.dec.ports() + self.e.ports()
 556
 557     def elaborate(self, platform):
 558         m = Module()
 559         comb = m.d.comb
 560         e, op = self.e, self.dec.op
 561
 562         # set up submodule decoders
 563         m.submodules.dec = self.dec
 564         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 565         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 566         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 567         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 568         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 569         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 570         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 571         m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
 572         m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
 573
 574         # copy instruction through...
 575         for i in [e.insn, dec_a.insn_in, dec_b.insn_in,
 576                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in, dec_rc.insn_in,
 577                   dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
 578             comb += i.eq(self.dec.opcode_in)
 579
 580         # ...and subdecoders' input fields
 581         comb += dec_a.sel_in.eq(op.in1_sel)
 582         comb += dec_b.sel_in.eq(op.in2_sel)
 583         comb += dec_c.sel_in.eq(op.in3_sel)
 584         comb += dec_o.sel_in.eq(op.out_sel)
 585         comb += dec_o2.sel_in.eq(op.out_sel)
 586         comb += dec_o2.lk.eq(e.lk)
 587         comb += dec_rc.sel_in.eq(op.rc_sel)
 588         comb += dec_oe.sel_in.eq(op.rc_sel) # XXX should be OE sel
 589         comb += dec_cr_in.sel_in.eq(op.cr_in)
 590         comb += dec_cr_out.sel_in.eq(op.cr_out)
 591         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 592
 593
 594         comb += e.nia.eq(0)    # XXX TODO (or remove? not sure yet)
 595         fu = op.function_unit
 596         itype = Mux(fu == Function.NONE, InternalOp.OP_ILLEGAL, op.internal_op)
 597         comb += e.insn_type.eq(itype)
 598         comb += e.fn_unit.eq(fu)
 599
 600         # registers a, b, c and out and out2 (LD/ST EA)
 601         comb += e.read_reg1.eq(dec_a.reg_out)
 602         comb += e.read_reg2.eq(dec_b.reg_out)
 603         comb += e.read_reg3.eq(dec_c.reg_out)
 604         comb += e.write_reg.eq(dec_o.reg_out)
 605         comb += e.write_ea.eq(dec_o2.reg_out)
 606         comb += e.imm_data.eq(dec_b.imm_out) # immediate in RB (usually)
 607         comb += e.zero_a.eq(dec_a.immz_out)  # RA==0 detected
 608
 609         # rc and oe out
 610         comb += e.rc.eq(dec_rc.rc_out)
 611         comb += e.oe.eq(dec_oe.oe_out)
 612
 613         # SPRs out
 614         comb += e.read_spr1.eq(dec_a.spr_out)
 615         comb += e.write_spr.eq(dec_o.spr_out)
 616
 617         # Fast regs out
 618         comb += e.read_fast1.eq(dec_a.fast_out)
 619         comb += e.read_fast2.eq(dec_b.fast_out)
 620         comb += e.write_fast1.eq(dec_o.fast_out)
 621         comb += e.write_fast2.eq(dec_o2.fast_out)
 622
 623         comb += e.read_cr1.eq(dec_cr_in.cr_bitfield)
 624         comb += e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
 625         comb += e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
 626         comb += e.read_cr_whole.eq(dec_cr_in.whole_reg)
 627
 628         comb += e.write_cr.eq(dec_cr_out.cr_bitfield)
 629         comb += e.write_cr_whole.eq(dec_cr_out.whole_reg)
 630
 631         # decoded/selected instruction flags
 632         comb += e.data_len.eq(op.ldst_len)
 633         comb += e.invert_a.eq(op.inv_a)
 634         comb += e.invert_out.eq(op.inv_out)
 635         comb += e.input_carry.eq(op.cry_in)   # carry comes in
 636         comb += e.output_carry.eq(op.cry_out) # carry goes out
 637         comb += e.is_32bit.eq(op.is_32b)
 638         comb += e.is_signed.eq(op.sgn)
 639         with m.If(op.lk):
 640             comb += e.lk.eq(self.dec.LK) # XXX TODO: accessor
 641
 642         comb += e.byte_reverse.eq(op.br)
 643         comb += e.sign_extend.eq(op.sgn_ext)
 644         comb += e.update.eq(op.upd) # LD/ST "update" mode.
 645
 646
 647         # These should be removed eventually
 648         comb += e.input_cr.eq(op.cr_in)   # condition reg comes in
 649         comb += e.output_cr.eq(op.cr_out) # condition reg goes in
 650
 651         return m
 652
 653         # privileged instruction
 654         with m.If(instr_is_priv(m, op.internal_op, e.insn) & msr[MSR_PR]):
 655             # don't request registers RA/RT
 656             comb += e.read_reg1.eq(0)
 657             comb += e.read_reg2.eq(0)
 658             comb += e.read_reg3.eq(0)
 659             comb += e.write_reg.eq(0)
 660             comb += e.write_ea.eq(0)
 661             # privileged instruction trap
 662             comb += op.internal_op.eq(InternalOp.OP_TRAP)
 663             comb += e.traptype.eq(TT_PRIV) # request privileged instruction
 664             comb += e.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
 665         return m
 666
 667     def regspecmap_read(self, regfile, regname):
 668         """regspecmap_read: provides PowerDecode2 with an encoding relationship
 669         to Function Unit port regfiles (read-enable, read regnum, write regnum)
 670         regfile and regname arguments are fields 1 and 2 from a given regspec.
 671         """
 672         return regspec_decode_read(self.e, regfile, regname)
 673
 674     def regspecmap_write(self, regfile, regname):
 675         """regspecmap_write: provides PowerDecode2 with an encoding relationship
 676         to Function Unit port regfiles (write port, write regnum)
 677         regfile and regname arguments are fields 1 and 2 from a given regspec.
 678         """
 679         return regspec_decode_write(self.e, regfile, regname)
 680
 681     def rdflags(self, cu):
 682         rdl = []
 683         for idx in range(cu.n_src):
 684             regfile, regname, _ = cu.get_in_spec(idx)
 685             rdflag, read = self.regspecmap_read(regfile, regname)
 686             rdl.append(rdflag)
 687         print ("rdflags", rdl)
 688         return Cat(*rdl)
 689
 690
 691 if __name__ == '__main__':
 692     pdecode = create_pdecode()
 693     dec2 = PowerDecode2(pdecode)
 694     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 695     with open("dec2.il", "w") as f:
 696         f.write(vl)
 697