Revert "ok ok - for OP_BCREG put CTR in spr2 as well"
[soc.git] / src / soc / decoder / power_decoder2.py
1 """Power ISA Decoder second stage
2
3 based on Anton Blanchard microwatt decode2.vhdl
4
5 """
6 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
7 from nmigen.cli import rtlil
8
9 from nmutil.iocontrol import RecordObject
10 from nmutil.extend import exts
11
12 from soc.decoder.power_regspec_map import regspec_decode
13 from soc.decoder.power_decoder import create_pdecode
14 from soc.decoder.power_enums import (InternalOp, CryIn, Function,
15 CRInSel, CROutSel,
16 LdstLen, In1Sel, In2Sel, In3Sel,
17 OutSel, SPR, RC)
18
19 from soc.regfile.regfiles import FastRegs
20
21 class DecodeA(Elaboratable):
22 """DecodeA from instruction
23
24 decodes register RA, whether immediate-zero, implicit and
25 explicit CSRs
26 """
27
28 def __init__(self, dec):
29 self.dec = dec
30 self.sel_in = Signal(In1Sel, reset_less=True)
31 self.insn_in = Signal(32, reset_less=True)
32 self.reg_out = Data(5, name="reg_a")
33 self.immz_out = Signal(reset_less=True)
34 self.spr_out = Data(10, "spr_a")
35 self.fast_out = Data(3, "fast_a")
36
37 def elaborate(self, platform):
38 m = Module()
39 comb = m.d.comb
40
41 # select Register A field
42 ra = Signal(5, reset_less=True)
43 comb += ra.eq(self.dec.RA)
44 with m.If((self.sel_in == In1Sel.RA) |
45 ((self.sel_in == In1Sel.RA_OR_ZERO) &
46 (ra != Const(0, 5)))):
47 comb += self.reg_out.data.eq(ra)
48 comb += self.reg_out.ok.eq(1)
49
50 # zero immediate requested
51 with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
52 (self.reg_out.data == Const(0, 5))):
53 comb += self.immz_out.eq(1)
54
55 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
56 with m.If(self.sel_in == In1Sel.RS):
57 comb += self.reg_out.data.eq(self.dec.RS)
58 comb += self.reg_out.ok.eq(1)
59
60 # decode Fast-SPR based on instruction type
61 op = self.dec.op
62 # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
63 with m.If(op.internal_op == InternalOp.OP_BC):
64 with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
65 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
66 comb += self.fast_out.ok.eq(1)
67 with m.Elif(op.internal_op == InternalOp.OP_BCREG):
68 xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
69 xo5 = self.dec.FormXL.XO[5] # 3.0B p38
70 with m.If(xo9 & ~xo5):
71 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
72 comb += self.fast_out.ok.eq(1)
73
74 # MFSPR or MTSPR: move-from / move-to SPRs
75 with m.If((op.internal_op == InternalOp.OP_MFSPR) |
76 (op.internal_op == InternalOp.OP_MTSPR)):
77 # XXX TODO: fast/slow SPR decoding and mapping
78 comb += self.spr_out.data.eq(self.dec.SPR) # SPR field, XFX
79 comb += self.spr_out.ok.eq(1)
80
81 return m
82
83
84 class Data(Record):
85
86 def __init__(self, width, name):
87 name_ok = "%s_ok" % name
88 layout = ((name, width), (name_ok, 1))
89 Record.__init__(self, layout)
90 self.data = getattr(self, name) # convenience
91 self.ok = getattr(self, name_ok) # convenience
92 self.data.reset_less = True # grrr
93 self.reset_less = True # grrr
94
95 def ports(self):
96 return [self.data, self.ok]
97
98
99 class DecodeB(Elaboratable):
100 """DecodeB from instruction
101
102 decodes register RB, different forms of immediate (signed, unsigned),
103 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
104 by industry-standard convention, "lane 2" is where fully-decoded
105 immediates are muxed in.
106 """
107
108 def __init__(self, dec):
109 self.dec = dec
110 self.sel_in = Signal(In2Sel, reset_less=True)
111 self.insn_in = Signal(32, reset_less=True)
112 self.reg_out = Data(5, "reg_b")
113 self.imm_out = Data(64, "imm_b")
114 self.fast_out = Data(3, "fast_b")
115
116 def elaborate(self, platform):
117 m = Module()
118 comb = m.d.comb
119
120 # select Register B field
121 with m.Switch(self.sel_in):
122 with m.Case(In2Sel.RB):
123 comb += self.reg_out.data.eq(self.dec.RB)
124 comb += self.reg_out.ok.eq(1)
125 with m.Case(In2Sel.RS):
126 comb += self.reg_out.data.eq(self.dec.RS) # for M-Form shiftrot
127 comb += self.reg_out.ok.eq(1)
128 with m.Case(In2Sel.CONST_UI):
129 comb += self.imm_out.data.eq(self.dec.UI)
130 comb += self.imm_out.ok.eq(1)
131 with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
132 comb += self.imm_out.data.eq(
133 exts(self.dec.SI, 16, 64))
134 comb += self.imm_out.ok.eq(1)
135 with m.Case(In2Sel.CONST_UI_HI):
136 comb += self.imm_out.data.eq(self.dec.UI<<16)
137 comb += self.imm_out.ok.eq(1)
138 with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
139 comb += self.imm_out.data.eq(self.dec.SI<<16)
140 comb += self.imm_out.data.eq(
141 exts(self.dec.SI << 16, 32, 64))
142 comb += self.imm_out.ok.eq(1)
143 with m.Case(In2Sel.CONST_LI):
144 comb += self.imm_out.data.eq(self.dec.LI<<2)
145 comb += self.imm_out.ok.eq(1)
146 with m.Case(In2Sel.CONST_BD):
147 comb += self.imm_out.data.eq(self.dec.BD<<2)
148 comb += self.imm_out.ok.eq(1)
149 with m.Case(In2Sel.CONST_DS):
150 comb += self.imm_out.data.eq(self.dec.DS<<2)
151 comb += self.imm_out.ok.eq(1)
152 with m.Case(In2Sel.CONST_M1):
153 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
154 comb += self.imm_out.ok.eq(1)
155 with m.Case(In2Sel.CONST_SH):
156 comb += self.imm_out.data.eq(self.dec.sh)
157 comb += self.imm_out.ok.eq(1)
158 with m.Case(In2Sel.CONST_SH32):
159 comb += self.imm_out.data.eq(self.dec.SH32)
160 comb += self.imm_out.ok.eq(1)
161
162 # decode SPR2 based on instruction type
163 op = self.dec.op
164 # BCREG implicitly uses LR or TAR for 2nd reg
165 # CTR however is already in fast_spr1 *not* 2.
166 with m.If(op.internal_op == InternalOp.OP_BCREG):
167 xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
168 xo5 = self.dec.FormXL.XO[5] # 3.0B p38
169 with m.If(~xo9):
170 comb += self.fast_out.data.eq(FastRegs.LR)
171 comb += self.fast_out.ok.eq(1)
172 with m.Elif(xo5):
173 comb += self.fast_out.data.eq(FastRegs.TAR)
174 comb += self.fast_out.ok.eq(1)
175
176 return m
177
178
179 class DecodeC(Elaboratable):
180 """DecodeC from instruction
181
182 decodes register RC. this is "lane 3" into some CompUnits (not many)
183 """
184
185 def __init__(self, dec):
186 self.dec = dec
187 self.sel_in = Signal(In3Sel, reset_less=True)
188 self.insn_in = Signal(32, reset_less=True)
189 self.reg_out = Data(5, "reg_c")
190
191 def elaborate(self, platform):
192 m = Module()
193 comb = m.d.comb
194
195 # select Register C field
196 with m.Switch(self.sel_in):
197 with m.Case(In3Sel.RB):
198 comb += self.reg_out.data.eq(self.dec.RB) # for M-Form shiftrot
199 comb += self.reg_out.ok.eq(1)
200 with m.Case(In3Sel.RS):
201 comb += self.reg_out.data.eq(self.dec.RS)
202 comb += self.reg_out.ok.eq(1)
203
204 return m
205
206
207 class DecodeOut(Elaboratable):
208 """DecodeOut from instruction
209
210 decodes output register RA, RT or SPR
211 """
212
213 def __init__(self, dec):
214 self.dec = dec
215 self.sel_in = Signal(OutSel, reset_less=True)
216 self.insn_in = Signal(32, reset_less=True)
217 self.reg_out = Data(5, "reg_o")
218 self.spr_out = Data(10, "spr_o")
219 self.fast_out = Data(3, "fast_o")
220
221 def elaborate(self, platform):
222 m = Module()
223 comb = m.d.comb
224
225 # select Register out field
226 with m.Switch(self.sel_in):
227 with m.Case(OutSel.RT):
228 comb += self.reg_out.data.eq(self.dec.RT)
229 comb += self.reg_out.ok.eq(1)
230 with m.Case(OutSel.RA):
231 comb += self.reg_out.data.eq(self.dec.RA)
232 comb += self.reg_out.ok.eq(1)
233 with m.Case(OutSel.SPR):
234 comb += self.spr_out.data.eq(self.dec.SPR) # from XFX
235 comb += self.spr_out.ok.eq(1)
236
237 # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
238 op = self.dec.op
239 with m.If((op.internal_op == InternalOp.OP_BC) |
240 (op.internal_op == InternalOp.OP_BCREG)):
241 with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
242 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
243 comb += self.fast_out.ok.eq(1)
244 return m
245
246
247 class DecodeOut2(Elaboratable):
248 """DecodeOut2 from instruction
249
250 decodes output registers
251 """
252
253 def __init__(self, dec):
254 self.dec = dec
255 self.sel_in = Signal(OutSel, reset_less=True)
256 self.insn_in = Signal(32, reset_less=True)
257 self.reg_out = Data(5, "reg_o")
258 self.fast_out = Data(3, "fast_o")
259
260 def elaborate(self, platform):
261 m = Module()
262 comb = m.d.comb
263
264 # update mode LD/ST uses read-reg A also as an output
265 with m.If(self.dec.op.upd):
266 comb += self.reg_out.eq(self.dec.RA)
267 comb += self.reg_out.ok.eq(1)
268
269 # BC or BCREG: potential implicit register (LR) output
270 op = self.dec.op
271 with m.If((op.internal_op == InternalOp.OP_BC) |
272 (op.internal_op == InternalOp.OP_BCREG)):
273 with m.If(self.dec.op.lk & self.dec.LK): # "link" mode
274 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
275 comb += self.fast_out.ok.eq(1)
276
277 return m
278
279
280 class DecodeRC(Elaboratable):
281 """DecodeRc from instruction
282
283 decodes Record bit Rc
284 """
285 def __init__(self, dec):
286 self.dec = dec
287 self.sel_in = Signal(RC, reset_less=True)
288 self.insn_in = Signal(32, reset_less=True)
289 self.rc_out = Data(1, "rc")
290
291 def elaborate(self, platform):
292 m = Module()
293 comb = m.d.comb
294
295 # select Record bit out field
296 with m.Switch(self.sel_in):
297 with m.Case(RC.RC):
298 comb += self.rc_out.data.eq(self.dec.Rc)
299 comb += self.rc_out.ok.eq(1)
300 with m.Case(RC.ONE):
301 comb += self.rc_out.data.eq(1)
302 comb += self.rc_out.ok.eq(1)
303 with m.Case(RC.NONE):
304 comb += self.rc_out.data.eq(0)
305 comb += self.rc_out.ok.eq(1)
306
307 return m
308
309
310 class DecodeOE(Elaboratable):
311 """DecodeOE from instruction
312
313 decodes OE field: uses RC decode detection which might not be good
314
315 -- For now, use "rc" in the decode table to decide whether oe exists.
316 -- This is not entirely correct architecturally: For mulhd and
317 -- mulhdu, the OE field is reserved. It remains to be seen what an
318 -- actual POWER9 does if we set it on those instructions, for now we
319 -- test that further down when assigning to the multiplier oe input.
320 """
321 def __init__(self, dec):
322 self.dec = dec
323 self.sel_in = Signal(RC, reset_less=True)
324 self.insn_in = Signal(32, reset_less=True)
325 self.oe_out = Data(1, "oe")
326
327 def elaborate(self, platform):
328 m = Module()
329 comb = m.d.comb
330
331 # select OE bit out field
332 with m.Switch(self.sel_in):
333 with m.Case(RC.RC):
334 comb += self.oe_out.data.eq(self.dec.OE)
335 comb += self.oe_out.ok.eq(1)
336
337 return m
338
339 class DecodeCRIn(Elaboratable):
340 """Decodes input CR from instruction
341
342 CR indices - insn fields - (not the data *in* the CR) require only 3
343 bits because they refer to CR0-CR7
344 """
345
346 def __init__(self, dec):
347 self.dec = dec
348 self.sel_in = Signal(CRInSel, reset_less=True)
349 self.insn_in = Signal(32, reset_less=True)
350 self.cr_bitfield = Data(3, "cr_bitfield")
351 self.cr_bitfield_b = Data(3, "cr_bitfield_b")
352 self.cr_bitfield_o = Data(3, "cr_bitfield_o")
353 self.whole_reg = Signal(reset_less=True)
354
355 def elaborate(self, platform):
356 m = Module()
357 comb = m.d.comb
358
359 comb += self.cr_bitfield.ok.eq(0)
360 comb += self.cr_bitfield_b.ok.eq(0)
361 comb += self.whole_reg.eq(0)
362 with m.Switch(self.sel_in):
363 with m.Case(CRInSel.NONE):
364 pass # No bitfield activated
365 with m.Case(CRInSel.CR0):
366 comb += self.cr_bitfield.data.eq(0)
367 comb += self.cr_bitfield.ok.eq(1)
368 with m.Case(CRInSel.BI):
369 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
370 comb += self.cr_bitfield.ok.eq(1)
371 with m.Case(CRInSel.BFA):
372 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
373 comb += self.cr_bitfield.ok.eq(1)
374 with m.Case(CRInSel.BA_BB):
375 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
376 comb += self.cr_bitfield.ok.eq(1)
377 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
378 comb += self.cr_bitfield_b.ok.eq(1)
379 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
380 comb += self.cr_bitfield_o.ok.eq(1)
381 with m.Case(CRInSel.BC):
382 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
383 comb += self.cr_bitfield.ok.eq(1)
384 with m.Case(CRInSel.WHOLE_REG):
385 comb += self.whole_reg.eq(1)
386
387 return m
388
389
390 class DecodeCROut(Elaboratable):
391 """Decodes input CR from instruction
392
393 CR indices - insn fields - (not the data *in* the CR) require only 3
394 bits because they refer to CR0-CR7
395 """
396
397 def __init__(self, dec):
398 self.dec = dec
399 self.rc_in = Signal(reset_less=True)
400 self.sel_in = Signal(CROutSel, reset_less=True)
401 self.insn_in = Signal(32, reset_less=True)
402 self.cr_bitfield = Data(3, "cr_bitfield")
403 self.whole_reg = Signal(reset_less=True)
404
405 def elaborate(self, platform):
406 m = Module()
407 comb = m.d.comb
408
409 comb += self.cr_bitfield.ok.eq(0)
410 comb += self.whole_reg.eq(0)
411 with m.Switch(self.sel_in):
412 with m.Case(CROutSel.NONE):
413 pass # No bitfield activated
414 with m.Case(CROutSel.CR0):
415 comb += self.cr_bitfield.data.eq(0)
416 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
417 with m.Case(CROutSel.BF):
418 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF[0:-1])
419 comb += self.cr_bitfield.ok.eq(1)
420 with m.Case(CROutSel.BT):
421 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
422 comb += self.cr_bitfield.ok.eq(1)
423 with m.Case(CROutSel.WHOLE_REG):
424 comb += self.whole_reg.eq(1)
425
426 return m
427
428
429 class XerBits:
430 def __init__(self):
431 self.ca = Signal(2, reset_less=True)
432 self.ov = Signal(2, reset_less=True)
433 self.so = Signal(reset_less=True)
434
435 def ports(self):
436 return [self.ca, self.ov, self.so]
437
438
439 class Decode2ToExecute1Type(RecordObject):
440
441 def __init__(self, name=None):
442
443 RecordObject.__init__(self, name=name)
444
445 self.valid = Signal(reset_less=True)
446 self.insn_type = Signal(InternalOp, reset_less=True)
447 self.fn_unit = Signal(Function, reset_less=True)
448 self.nia = Signal(64, reset_less=True)
449 self.write_reg = Data(5, name="rego")
450 self.write_ea = Data(5, name="ea") # for LD/ST in update mode
451 self.read_reg1 = Data(5, name="reg1")
452 self.read_reg2 = Data(5, name="reg2")
453 self.read_reg3 = Data(5, name="reg3")
454 self.imm_data = Data(64, name="imm")
455 self.write_spr = Data(10, name="spro")
456 self.read_spr1 = Data(10, name="spr1")
457 self.read_spr2 = Data(10, name="spr2")
458
459 self.read_fast1 = Data(3, name="fast1")
460 self.read_fast2 = Data(3, name="fast2")
461 self.write_fast1 = Data(3, name="fasto1")
462 self.write_fast2 = Data(3, name="fasto2")
463
464 self.read_cr1 = Data(3, name="cr_in1")
465 self.read_cr2 = Data(3, name="cr_in2")
466 self.read_cr3 = Data(3, name="cr_in2")
467 self.read_cr_whole = Signal(reset_less=True)
468 self.write_cr = Data(3, name="cr_out")
469 self.write_cr_whole = Signal(reset_less=True)
470 self.lk = Signal(reset_less=True)
471 self.rc = Data(1, "rc")
472 self.oe = Data(1, "oe")
473 self.invert_a = Signal(reset_less=True)
474 self.zero_a = Signal(reset_less=True)
475 self.invert_out = Signal(reset_less=True)
476 self.input_carry = Signal(CryIn, reset_less=True)
477 self.output_carry = Signal(reset_less=True)
478 self.input_cr = Signal(reset_less=True) # instr. has a CR as input
479 self.output_cr = Signal(reset_less=True) # instr. has a CR as output
480 self.is_32bit = Signal(reset_less=True)
481 self.is_signed = Signal(reset_less=True)
482 self.insn = Signal(32, reset_less=True)
483 self.data_len = Signal(4, reset_less=True) # bytes
484 self.byte_reverse = Signal(reset_less=True)
485 self.sign_extend = Signal(reset_less=True)# do we need this?
486 self.update = Signal(reset_less=True) # LD/ST is "update" variant
487
488
489 class PowerDecode2(Elaboratable):
490
491 def __init__(self, dec):
492
493 self.dec = dec
494 self.e = Decode2ToExecute1Type()
495
496 def ports(self):
497 return self.dec.ports() + self.e.ports()
498
499 def elaborate(self, platform):
500 m = Module()
501 comb = m.d.comb
502
503 # set up submodule decoders
504 m.submodules.dec = self.dec
505 m.submodules.dec_a = dec_a = DecodeA(self.dec)
506 m.submodules.dec_b = dec_b = DecodeB(self.dec)
507 m.submodules.dec_c = dec_c = DecodeC(self.dec)
508 m.submodules.dec_o = dec_o = DecodeOut(self.dec)
509 m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
510 m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
511 m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
512 m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
513 m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
514
515 # copy instruction through...
516 for i in [self.e.insn, dec_a.insn_in, dec_b.insn_in,
517 dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in, dec_rc.insn_in,
518 dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
519 comb += i.eq(self.dec.opcode_in)
520
521 # ...and subdecoders' input fields
522 comb += dec_a.sel_in.eq(self.dec.op.in1_sel)
523 comb += dec_b.sel_in.eq(self.dec.op.in2_sel)
524 comb += dec_c.sel_in.eq(self.dec.op.in3_sel)
525 comb += dec_o.sel_in.eq(self.dec.op.out_sel)
526 comb += dec_o2.sel_in.eq(self.dec.op.out_sel)
527 comb += dec_rc.sel_in.eq(self.dec.op.rc_sel)
528 comb += dec_oe.sel_in.eq(self.dec.op.rc_sel) # XXX should be OE sel
529 comb += dec_cr_in.sel_in.eq(self.dec.op.cr_in)
530 comb += dec_cr_out.sel_in.eq(self.dec.op.cr_out)
531 comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
532
533 # decode LD/ST length
534 with m.Switch(self.dec.op.ldst_len):
535 with m.Case(LdstLen.is1B):
536 comb += self.e.data_len.eq(1)
537 with m.Case(LdstLen.is2B):
538 comb += self.e.data_len.eq(2)
539 with m.Case(LdstLen.is4B):
540 comb += self.e.data_len.eq(4)
541 with m.Case(LdstLen.is8B):
542 comb += self.e.data_len.eq(8)
543
544 comb += self.e.nia.eq(0) # XXX TODO
545 comb += self.e.valid.eq(0) # XXX TODO
546 fu = self.dec.op.function_unit
547 itype = Mux(fu == Function.NONE,
548 InternalOp.OP_ILLEGAL,
549 self.dec.op.internal_op)
550 comb += self.e.insn_type.eq(itype)
551 comb += self.e.fn_unit.eq(fu)
552
553 # registers a, b, c and out and out2 (LD/ST EA)
554 comb += self.e.read_reg1.eq(dec_a.reg_out)
555 comb += self.e.read_reg2.eq(dec_b.reg_out)
556 comb += self.e.read_reg3.eq(dec_c.reg_out)
557 comb += self.e.write_reg.eq(dec_o.reg_out)
558 comb += self.e.write_ea.eq(dec_o2.reg_out)
559 comb += self.e.imm_data.eq(dec_b.imm_out) # immediate in RB (usually)
560 comb += self.e.zero_a.eq(dec_a.immz_out) # RA==0 detected
561
562 # rc and oe out
563 comb += self.e.rc.eq(dec_rc.rc_out)
564 comb += self.e.oe.eq(dec_oe.oe_out)
565
566 # SPRs out
567 comb += self.e.read_spr1.eq(dec_a.spr_out)
568 comb += self.e.write_spr.eq(dec_o.spr_out)
569
570 # Fast regs out
571 comb += self.e.read_fast1.eq(dec_a.fast_out)
572 comb += self.e.read_fast2.eq(dec_b.fast_out)
573 comb += self.e.write_fast1.eq(dec_o.fast_out)
574 comb += self.e.write_fast2.eq(dec_o2.fast_out)
575
576 comb += self.e.read_cr1.eq(dec_cr_in.cr_bitfield)
577 comb += self.e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
578 comb += self.e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
579 comb += self.e.read_cr_whole.eq(dec_cr_in.whole_reg)
580
581 comb += self.e.write_cr.eq(dec_cr_out.cr_bitfield)
582 comb += self.e.write_cr_whole.eq(dec_cr_out.whole_reg)
583
584 # decoded/selected instruction flags
585 comb += self.e.invert_a.eq(self.dec.op.inv_a)
586 comb += self.e.invert_out.eq(self.dec.op.inv_out)
587 comb += self.e.input_carry.eq(self.dec.op.cry_in) # carry comes in
588 comb += self.e.output_carry.eq(self.dec.op.cry_out) # carry goes out
589 comb += self.e.is_32bit.eq(self.dec.op.is_32b)
590 comb += self.e.is_signed.eq(self.dec.op.sgn)
591 with m.If(self.dec.op.lk):
592 comb += self.e.lk.eq(self.dec.LK) # XXX TODO: accessor
593
594 comb += self.e.byte_reverse.eq(self.dec.op.br)
595 comb += self.e.sign_extend.eq(self.dec.op.sgn_ext)
596 comb += self.e.update.eq(self.dec.op.upd) # LD/ST "update" mode.
597
598
599 # These should be removed eventually
600 comb += self.e.input_cr.eq(self.dec.op.cr_in) # condition reg comes in
601 comb += self.e.output_cr.eq(self.dec.op.cr_out) # condition reg goes in
602
603
604 return m
605
606 def regspecmap(self, regfile, regname):
607 """regspecmap: provides PowerDecode2 with an encoding relationship
608 to Function Unit port regfiles (read-enable, read regnum, write regnum)
609 regfile and regname arguments are fields 1 and 2 from a given regspec.
610 """
611 return regspec_decode(self, regfile, regname)
612
613
614 if __name__ == '__main__':
615 pdecode = create_pdecode()
616 dec2 = PowerDecode2(pdecode)
617 vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
618 with open("dec2.il", "w") as f:
619 f.write(vl)
620