src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
   7 from nmigen.cli import rtlil
   8
   9 from nmutil.iocontrol import RecordObject
  10 from nmutil.extend import exts
  11
  12 from soc.decoder.power_regspec_map import regspec_decode
  13 from soc.decoder.power_decoder import create_pdecode
  14 from soc.decoder.power_enums import (InternalOp, CryIn, Function,
  15                                      CRInSel, CROutSel,
  16                                      LdstLen, In1Sel, In2Sel, In3Sel,
  17                                      OutSel, SPR, RC)
  18
  19 from soc.regfile.regfiles import FastRegs
  20
  21 class DecodeA(Elaboratable):
  22     """DecodeA from instruction
  23
  24     decodes register RA, whether immediate-zero, implicit and
  25     explicit CSRs
  26     """
  27
  28     def __init__(self, dec):
  29         self.dec = dec
  30         self.sel_in = Signal(In1Sel, reset_less=True)
  31         self.insn_in = Signal(32, reset_less=True)
  32         self.reg_out = Data(5, name="reg_a")
  33         self.immz_out = Signal(reset_less=True)
  34         self.spr_out = Data(10, "spr_a")
  35         self.fast_out = Data(3, "fast_a")
  36
  37     def elaborate(self, platform):
  38         m = Module()
  39         comb = m.d.comb
  40
  41         # select Register A field
  42         ra = Signal(5, reset_less=True)
  43         comb += ra.eq(self.dec.RA)
  44         with m.If((self.sel_in == In1Sel.RA) |
  45                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  46                    (ra != Const(0, 5)))):
  47             comb += self.reg_out.data.eq(ra)
  48             comb += self.reg_out.ok.eq(1)
  49
  50         # zero immediate requested
  51         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
  52                   (self.reg_out.data == Const(0, 5))):
  53             comb += self.immz_out.eq(1)
  54
  55         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
  56         with m.If(self.sel_in == In1Sel.RS):
  57             comb += self.reg_out.data.eq(self.dec.RS)
  58             comb += self.reg_out.ok.eq(1)
  59
  60         # decode Fast-SPR based on instruction type
  61         op = self.dec.op
  62         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
  63         with m.If(op.internal_op == InternalOp.OP_BC):
  64             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
  65                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
  66                 comb += self.fast_out.ok.eq(1)
  67         with m.Elif(op.internal_op == InternalOp.OP_BCREG):
  68             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
  69             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
  70             with m.If(xo9 & ~xo5):
  71                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
  72                 comb += self.fast_out.ok.eq(1)
  73
  74         # MFSPR or MTSPR: move-from / move-to SPRs
  75         with m.If((op.internal_op == InternalOp.OP_MFSPR) |
  76                   (op.internal_op == InternalOp.OP_MTSPR)):
  77             # XXX TODO: fast/slow SPR decoding and mapping
  78             comb += self.spr_out.data.eq(self.dec.SPR) # SPR field, XFX
  79             comb += self.spr_out.ok.eq(1)
  80
  81         return m
  82
  83
  84 class Data(Record):
  85
  86     def __init__(self, width, name):
  87         name_ok = "%s_ok" % name
  88         layout = ((name, width), (name_ok, 1))
  89         Record.__init__(self, layout)
  90         self.data = getattr(self, name) # convenience
  91         self.ok = getattr(self, name_ok) # convenience
  92         self.data.reset_less = True # grrr
  93         self.reset_less = True # grrr
  94
  95     def ports(self):
  96         return [self.data, self.ok]
  97
  98
  99 class DecodeB(Elaboratable):
 100     """DecodeB from instruction
 101
 102     decodes register RB, different forms of immediate (signed, unsigned),
 103     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 104     by industry-standard convention, "lane 2" is where fully-decoded
 105     immediates are muxed in.
 106     """
 107
 108     def __init__(self, dec):
 109         self.dec = dec
 110         self.sel_in = Signal(In2Sel, reset_less=True)
 111         self.insn_in = Signal(32, reset_less=True)
 112         self.reg_out = Data(5, "reg_b")
 113         self.imm_out = Data(64, "imm_b")
 114         self.fast_out = Data(3, "fast_b")
 115
 116     def elaborate(self, platform):
 117         m = Module()
 118         comb = m.d.comb
 119
 120         # select Register B field
 121         with m.Switch(self.sel_in):
 122             with m.Case(In2Sel.RB):
 123                 comb += self.reg_out.data.eq(self.dec.RB)
 124                 comb += self.reg_out.ok.eq(1)
 125             with m.Case(In2Sel.RS):
 126                 comb += self.reg_out.data.eq(self.dec.RS) # for M-Form shiftrot
 127                 comb += self.reg_out.ok.eq(1)
 128             with m.Case(In2Sel.CONST_UI):
 129                 comb += self.imm_out.data.eq(self.dec.UI)
 130                 comb += self.imm_out.ok.eq(1)
 131             with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
 132                 comb += self.imm_out.data.eq(
 133                     exts(self.dec.SI, 16, 64))
 134                 comb += self.imm_out.ok.eq(1)
 135             with m.Case(In2Sel.CONST_UI_HI):
 136                 comb += self.imm_out.data.eq(self.dec.UI<<16)
 137                 comb += self.imm_out.ok.eq(1)
 138             with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
 139                 comb += self.imm_out.data.eq(self.dec.SI<<16)
 140                 comb += self.imm_out.data.eq(
 141                     exts(self.dec.SI << 16, 32, 64))
 142                 comb += self.imm_out.ok.eq(1)
 143             with m.Case(In2Sel.CONST_LI):
 144                 comb += self.imm_out.data.eq(self.dec.LI<<2)
 145                 comb += self.imm_out.ok.eq(1)
 146             with m.Case(In2Sel.CONST_BD):
 147                 comb += self.imm_out.data.eq(self.dec.BD<<2)
 148                 comb += self.imm_out.ok.eq(1)
 149             with m.Case(In2Sel.CONST_DS):
 150                 comb += self.imm_out.data.eq(self.dec.DS<<2)
 151                 comb += self.imm_out.ok.eq(1)
 152             with m.Case(In2Sel.CONST_M1):
 153                 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
 154                 comb += self.imm_out.ok.eq(1)
 155             with m.Case(In2Sel.CONST_SH):
 156                 comb += self.imm_out.data.eq(self.dec.sh)
 157                 comb += self.imm_out.ok.eq(1)
 158             with m.Case(In2Sel.CONST_SH32):
 159                 comb += self.imm_out.data.eq(self.dec.SH32)
 160                 comb += self.imm_out.ok.eq(1)
 161
 162         # decode SPR2 based on instruction type
 163         op = self.dec.op
 164         # BCREG implicitly uses LR or TAR for 2nd reg
 165         # CTR however is already in fast_spr1 *not* 2.
 166         with m.If(op.internal_op == InternalOp.OP_BCREG):
 167             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
 168             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
 169             with m.If(~xo9):
 170                 comb += self.fast_out.data.eq(FastRegs.LR)
 171                 comb += self.fast_out.ok.eq(1)
 172             with m.Elif(xo5):
 173                 comb += self.fast_out.data.eq(FastRegs.TAR)
 174                 comb += self.fast_out.ok.eq(1)
 175
 176         return m
 177
 178
 179 class DecodeC(Elaboratable):
 180     """DecodeC from instruction
 181
 182     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 183     """
 184
 185     def __init__(self, dec):
 186         self.dec = dec
 187         self.sel_in = Signal(In3Sel, reset_less=True)
 188         self.insn_in = Signal(32, reset_less=True)
 189         self.reg_out = Data(5, "reg_c")
 190
 191     def elaborate(self, platform):
 192         m = Module()
 193         comb = m.d.comb
 194
 195         # select Register C field
 196         with m.Switch(self.sel_in):
 197             with m.Case(In3Sel.RB):
 198                 comb += self.reg_out.data.eq(self.dec.RB) # for M-Form shiftrot
 199                 comb += self.reg_out.ok.eq(1)
 200             with m.Case(In3Sel.RS):
 201                 comb += self.reg_out.data.eq(self.dec.RS)
 202                 comb += self.reg_out.ok.eq(1)
 203
 204         return m
 205
 206
 207 class DecodeOut(Elaboratable):
 208     """DecodeOut from instruction
 209
 210     decodes output register RA, RT or SPR
 211     """
 212
 213     def __init__(self, dec):
 214         self.dec = dec
 215         self.sel_in = Signal(OutSel, reset_less=True)
 216         self.insn_in = Signal(32, reset_less=True)
 217         self.reg_out = Data(5, "reg_o")
 218         self.spr_out = Data(10, "spr_o")
 219         self.fast_out = Data(3, "fast_o")
 220
 221     def elaborate(self, platform):
 222         m = Module()
 223         comb = m.d.comb
 224
 225         # select Register out field
 226         with m.Switch(self.sel_in):
 227             with m.Case(OutSel.RT):
 228                 comb += self.reg_out.data.eq(self.dec.RT)
 229                 comb += self.reg_out.ok.eq(1)
 230             with m.Case(OutSel.RA):
 231                 comb += self.reg_out.data.eq(self.dec.RA)
 232                 comb += self.reg_out.ok.eq(1)
 233             with m.Case(OutSel.SPR):
 234                 comb += self.spr_out.data.eq(self.dec.SPR) # from XFX
 235                 comb += self.spr_out.ok.eq(1)
 236
 237         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
 238         op = self.dec.op
 239         with m.If((op.internal_op == InternalOp.OP_BC) |
 240                   (op.internal_op == InternalOp.OP_BCREG)):
 241             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
 242                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
 243                 comb += self.fast_out.ok.eq(1)
 244         return m
 245
 246
 247 class DecodeOut2(Elaboratable):
 248     """DecodeOut2 from instruction
 249
 250     decodes output registers
 251     """
 252
 253     def __init__(self, dec):
 254         self.dec = dec
 255         self.sel_in = Signal(OutSel, reset_less=True)
 256         self.lk = Signal(reset_less=True)
 257         self.insn_in = Signal(32, reset_less=True)
 258         self.reg_out = Data(5, "reg_o")
 259         self.fast_out = Data(3, "fast_o")
 260
 261     def elaborate(self, platform):
 262         m = Module()
 263         comb = m.d.comb
 264
 265         # update mode LD/ST uses read-reg A also as an output
 266         with m.If(self.dec.op.upd):
 267             comb += self.reg_out.eq(self.dec.RA)
 268             comb += self.reg_out.ok.eq(1)
 269
 270         # BC or BCREG: potential implicit register (LR) output
 271         op = self.dec.op
 272         with m.If((op.internal_op == InternalOp.OP_BC) |
 273                   (op.internal_op == InternalOp.OP_BCREG)):
 274             with m.If(self.lk): # "link" mode
 275                 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
 276                 comb += self.fast_out.ok.eq(1)
 277
 278         return m
 279
 280
 281 class DecodeRC(Elaboratable):
 282     """DecodeRc from instruction
 283
 284     decodes Record bit Rc
 285     """
 286     def __init__(self, dec):
 287         self.dec = dec
 288         self.sel_in = Signal(RC, reset_less=True)
 289         self.insn_in = Signal(32, reset_less=True)
 290         self.rc_out = Data(1, "rc")
 291
 292     def elaborate(self, platform):
 293         m = Module()
 294         comb = m.d.comb
 295
 296         # select Record bit out field
 297         with m.Switch(self.sel_in):
 298             with m.Case(RC.RC):
 299                 comb += self.rc_out.data.eq(self.dec.Rc)
 300                 comb += self.rc_out.ok.eq(1)
 301             with m.Case(RC.ONE):
 302                 comb += self.rc_out.data.eq(1)
 303                 comb += self.rc_out.ok.eq(1)
 304             with m.Case(RC.NONE):
 305                 comb += self.rc_out.data.eq(0)
 306                 comb += self.rc_out.ok.eq(1)
 307
 308         return m
 309
 310
 311 class DecodeOE(Elaboratable):
 312     """DecodeOE from instruction
 313
 314     decodes OE field: uses RC decode detection which might not be good
 315
 316     -- For now, use "rc" in the decode table to decide whether oe exists.
 317     -- This is not entirely correct architecturally: For mulhd and
 318     -- mulhdu, the OE field is reserved. It remains to be seen what an
 319     -- actual POWER9 does if we set it on those instructions, for now we
 320     -- test that further down when assigning to the multiplier oe input.
 321     """
 322     def __init__(self, dec):
 323         self.dec = dec
 324         self.sel_in = Signal(RC, reset_less=True)
 325         self.insn_in = Signal(32, reset_less=True)
 326         self.oe_out = Data(1, "oe")
 327
 328     def elaborate(self, platform):
 329         m = Module()
 330         comb = m.d.comb
 331
 332         # select OE bit out field
 333         with m.Switch(self.sel_in):
 334             with m.Case(RC.RC):
 335                 comb += self.oe_out.data.eq(self.dec.OE)
 336                 comb += self.oe_out.ok.eq(1)
 337
 338         return m
 339
 340 class DecodeCRIn(Elaboratable):
 341     """Decodes input CR from instruction
 342
 343     CR indices - insn fields - (not the data *in* the CR) require only 3
 344     bits because they refer to CR0-CR7
 345     """
 346
 347     def __init__(self, dec):
 348         self.dec = dec
 349         self.sel_in = Signal(CRInSel, reset_less=True)
 350         self.insn_in = Signal(32, reset_less=True)
 351         self.cr_bitfield = Data(3, "cr_bitfield")
 352         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 353         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 354         self.whole_reg = Signal(reset_less=True)
 355
 356     def elaborate(self, platform):
 357         m = Module()
 358         comb = m.d.comb
 359
 360         comb += self.cr_bitfield.ok.eq(0)
 361         comb += self.cr_bitfield_b.ok.eq(0)
 362         comb += self.whole_reg.eq(0)
 363         with m.Switch(self.sel_in):
 364             with m.Case(CRInSel.NONE):
 365                 pass # No bitfield activated
 366             with m.Case(CRInSel.CR0):
 367                 comb += self.cr_bitfield.data.eq(0)
 368                 comb += self.cr_bitfield.ok.eq(1)
 369             with m.Case(CRInSel.BI):
 370                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 371                 comb += self.cr_bitfield.ok.eq(1)
 372             with m.Case(CRInSel.BFA):
 373                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 374                 comb += self.cr_bitfield.ok.eq(1)
 375             with m.Case(CRInSel.BA_BB):
 376                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 377                 comb += self.cr_bitfield.ok.eq(1)
 378                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 379                 comb += self.cr_bitfield_b.ok.eq(1)
 380                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 381                 comb += self.cr_bitfield_o.ok.eq(1)
 382             with m.Case(CRInSel.BC):
 383                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 384                 comb += self.cr_bitfield.ok.eq(1)
 385             with m.Case(CRInSel.WHOLE_REG):
 386                 comb += self.whole_reg.eq(1)
 387
 388         return m
 389
 390
 391 class DecodeCROut(Elaboratable):
 392     """Decodes input CR from instruction
 393
 394     CR indices - insn fields - (not the data *in* the CR) require only 3
 395     bits because they refer to CR0-CR7
 396     """
 397
 398     def __init__(self, dec):
 399         self.dec = dec
 400         self.rc_in = Signal(reset_less=True)
 401         self.sel_in = Signal(CROutSel, reset_less=True)
 402         self.insn_in = Signal(32, reset_less=True)
 403         self.cr_bitfield = Data(3, "cr_bitfield")
 404         self.whole_reg = Signal(reset_less=True)
 405
 406     def elaborate(self, platform):
 407         m = Module()
 408         comb = m.d.comb
 409
 410         comb += self.cr_bitfield.ok.eq(0)
 411         comb += self.whole_reg.eq(0)
 412         with m.Switch(self.sel_in):
 413             with m.Case(CROutSel.NONE):
 414                 pass # No bitfield activated
 415             with m.Case(CROutSel.CR0):
 416                 comb += self.cr_bitfield.data.eq(0)
 417                 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
 418             with m.Case(CROutSel.BF):
 419                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF[0:-1])
 420                 comb += self.cr_bitfield.ok.eq(1)
 421             with m.Case(CROutSel.BT):
 422                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 423                 comb += self.cr_bitfield.ok.eq(1)
 424             with m.Case(CROutSel.WHOLE_REG):
 425                 comb += self.whole_reg.eq(1)
 426
 427         return m
 428
 429
 430 class XerBits:
 431     def __init__(self):
 432         self.ca = Signal(2, reset_less=True)
 433         self.ov = Signal(2, reset_less=True)
 434         self.so = Signal(reset_less=True)
 435
 436     def ports(self):
 437         return [self.ca, self.ov, self.so]
 438
 439
 440 class Decode2ToExecute1Type(RecordObject):
 441
 442     def __init__(self, name=None):
 443
 444         RecordObject.__init__(self, name=name)
 445
 446         self.valid = Signal(reset_less=True)
 447         self.insn_type = Signal(InternalOp, reset_less=True)
 448         self.fn_unit = Signal(Function, reset_less=True)
 449         self.nia = Signal(64, reset_less=True)
 450         self.write_reg = Data(5, name="rego")
 451         self.write_ea = Data(5, name="ea") # for LD/ST in update mode
 452         self.read_reg1 = Data(5, name="reg1")
 453         self.read_reg2 = Data(5, name="reg2")
 454         self.read_reg3 = Data(5, name="reg3")
 455         self.imm_data = Data(64, name="imm")
 456         self.write_spr = Data(10, name="spro")
 457         self.read_spr1 = Data(10, name="spr1")
 458         self.read_spr2 = Data(10, name="spr2")
 459
 460         self.read_fast1 = Data(3, name="fast1")
 461         self.read_fast2 = Data(3, name="fast2")
 462         self.write_fast1 = Data(3, name="fasto1")
 463         self.write_fast2 = Data(3, name="fasto2")
 464
 465         self.read_cr1 = Data(3, name="cr_in1")
 466         self.read_cr2 = Data(3, name="cr_in2")
 467         self.read_cr3 = Data(3, name="cr_in2")
 468         self.read_cr_whole = Signal(reset_less=True)
 469         self.write_cr = Data(3, name="cr_out")
 470         self.write_cr_whole = Signal(reset_less=True)
 471         self.lk = Signal(reset_less=True)
 472         self.rc = Data(1, "rc")
 473         self.oe = Data(1, "oe")
 474         self.invert_a = Signal(reset_less=True)
 475         self.zero_a = Signal(reset_less=True)
 476         self.invert_out = Signal(reset_less=True)
 477         self.input_carry = Signal(CryIn, reset_less=True)
 478         self.output_carry = Signal(reset_less=True)
 479         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
 480         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
 481         self.is_32bit = Signal(reset_less=True)
 482         self.is_signed = Signal(reset_less=True)
 483         self.insn = Signal(32, reset_less=True)
 484         self.data_len = Signal(4, reset_less=True) # bytes
 485         self.byte_reverse  = Signal(reset_less=True)
 486         self.sign_extend  = Signal(reset_less=True)# do we need this?
 487         self.update  = Signal(reset_less=True) # LD/ST is "update" variant
 488
 489
 490 class PowerDecode2(Elaboratable):
 491
 492     def __init__(self, dec):
 493
 494         self.dec = dec
 495         self.e = Decode2ToExecute1Type()
 496
 497     def ports(self):
 498         return self.dec.ports() + self.e.ports()
 499
 500     def elaborate(self, platform):
 501         m = Module()
 502         comb = m.d.comb
 503
 504         # set up submodule decoders
 505         m.submodules.dec = self.dec
 506         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 507         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 508         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 509         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 510         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 511         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 512         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 513         m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
 514         m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
 515
 516         # copy instruction through...
 517         for i in [self.e.insn, dec_a.insn_in, dec_b.insn_in,
 518                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in, dec_rc.insn_in,
 519                   dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
 520             comb += i.eq(self.dec.opcode_in)
 521
 522         # ...and subdecoders' input fields
 523         comb += dec_a.sel_in.eq(self.dec.op.in1_sel)
 524         comb += dec_b.sel_in.eq(self.dec.op.in2_sel)
 525         comb += dec_c.sel_in.eq(self.dec.op.in3_sel)
 526         comb += dec_o.sel_in.eq(self.dec.op.out_sel)
 527         comb += dec_o2.sel_in.eq(self.dec.op.out_sel)
 528         comb += dec_o2.lk.eq(self.e.lk)
 529         comb += dec_rc.sel_in.eq(self.dec.op.rc_sel)
 530         comb += dec_oe.sel_in.eq(self.dec.op.rc_sel) # XXX should be OE sel
 531         comb += dec_cr_in.sel_in.eq(self.dec.op.cr_in)
 532         comb += dec_cr_out.sel_in.eq(self.dec.op.cr_out)
 533         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 534
 535         # decode LD/ST length
 536         with m.Switch(self.dec.op.ldst_len):
 537             with m.Case(LdstLen.is1B):
 538                 comb += self.e.data_len.eq(1)
 539             with m.Case(LdstLen.is2B):
 540                 comb += self.e.data_len.eq(2)
 541             with m.Case(LdstLen.is4B):
 542                 comb += self.e.data_len.eq(4)
 543             with m.Case(LdstLen.is8B):
 544                 comb += self.e.data_len.eq(8)
 545
 546         comb += self.e.nia.eq(0)    # XXX TODO
 547         fu = self.dec.op.function_unit
 548         itype = Mux(fu == Function.NONE,
 549                     InternalOp.OP_ILLEGAL,
 550                     self.dec.op.internal_op)
 551         comb += self.e.insn_type.eq(itype)
 552         comb += self.e.fn_unit.eq(fu)
 553
 554         # registers a, b, c and out and out2 (LD/ST EA)
 555         comb += self.e.read_reg1.eq(dec_a.reg_out)
 556         comb += self.e.read_reg2.eq(dec_b.reg_out)
 557         comb += self.e.read_reg3.eq(dec_c.reg_out)
 558         comb += self.e.write_reg.eq(dec_o.reg_out)
 559         comb += self.e.write_ea.eq(dec_o2.reg_out)
 560         comb += self.e.imm_data.eq(dec_b.imm_out) # immediate in RB (usually)
 561         comb += self.e.zero_a.eq(dec_a.immz_out)  # RA==0 detected
 562
 563         # rc and oe out
 564         comb += self.e.rc.eq(dec_rc.rc_out)
 565         comb += self.e.oe.eq(dec_oe.oe_out)
 566
 567         # SPRs out
 568         comb += self.e.read_spr1.eq(dec_a.spr_out)
 569         comb += self.e.write_spr.eq(dec_o.spr_out)
 570
 571         # Fast regs out
 572         comb += self.e.read_fast1.eq(dec_a.fast_out)
 573         comb += self.e.read_fast2.eq(dec_b.fast_out)
 574         comb += self.e.write_fast1.eq(dec_o.fast_out)
 575         comb += self.e.write_fast2.eq(dec_o2.fast_out)
 576
 577         comb += self.e.read_cr1.eq(dec_cr_in.cr_bitfield)
 578         comb += self.e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
 579         comb += self.e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
 580         comb += self.e.read_cr_whole.eq(dec_cr_in.whole_reg)
 581
 582         comb += self.e.write_cr.eq(dec_cr_out.cr_bitfield)
 583         comb += self.e.write_cr_whole.eq(dec_cr_out.whole_reg)
 584
 585         # decoded/selected instruction flags
 586         comb += self.e.invert_a.eq(self.dec.op.inv_a)
 587         comb += self.e.invert_out.eq(self.dec.op.inv_out)
 588         comb += self.e.input_carry.eq(self.dec.op.cry_in)   # carry comes in
 589         comb += self.e.output_carry.eq(self.dec.op.cry_out) # carry goes out
 590         comb += self.e.is_32bit.eq(self.dec.op.is_32b)
 591         comb += self.e.is_signed.eq(self.dec.op.sgn)
 592         with m.If(self.dec.op.lk):
 593             comb += self.e.lk.eq(self.dec.LK) # XXX TODO: accessor
 594
 595         comb += self.e.byte_reverse.eq(self.dec.op.br)
 596         comb += self.e.sign_extend.eq(self.dec.op.sgn_ext)
 597         comb += self.e.update.eq(self.dec.op.upd) # LD/ST "update" mode.
 598
 599
 600         # These should be removed eventually
 601         comb += self.e.input_cr.eq(self.dec.op.cr_in)   # condition reg comes in
 602         comb += self.e.output_cr.eq(self.dec.op.cr_out) # condition reg goes in
 603
 604
 605         return m
 606
 607     def regspecmap(self, regfile, regname):
 608         """regspecmap: provides PowerDecode2 with an encoding relationship
 609         to Function Unit port regfiles (read-enable, read regnum, write regnum)
 610         regfile and regname arguments are fields 1 and 2 from a given regspec.
 611         """
 612         return regspec_decode(self.e, regfile, regname)
 613
 614     def rdflags(self, cu):
 615         rdl = []
 616         for idx in range(cu.n_src):
 617             regfile, regname, _ = cu.get_in_spec(idx)
 618             rdflag, read, write = self.regspecmap(regfile, regname)
 619             rdl.append(rdflag)
 620         print ("rdflags", rdl)
 621         return Cat(*rdl)
 622
 623
 624 if __name__ == '__main__':
 625     pdecode = create_pdecode()
 626     dec2 = PowerDecode2(pdecode)
 627     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 628     with open("dec2.il", "w") as f:
 629         f.write(vl)
 630