create initial SimRunner
[soc.git] / src / soc / experiment / compalu_multi.py
1 """Computation Unit (aka "ALU Manager").
2
3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
4 monitored. At no time may the ALU proceed without this module notifying
5 the Dependency Matrices. At no time is a result production "abandoned".
6 This module blocks (indicates busy) starting from when it first receives
7 an opcode until it receives notification that
8 its result(s) have been successfully stored in the regfile(s)
9
10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
11 """
12
13 from nmigen import Module, Signal, Mux, Elaboratable, Repl, Cat, Const
14 from nmigen.hdl.rec import (Record, DIR_FANIN, DIR_FANOUT)
15
16 from nmutil.latch import SRLatch, latchregister
17 from nmutil.iocontrol import RecordObject
18 from nmutil.util import rising_edge
19
20 from soc.fu.regspec import RegSpec, RegSpecALUAPI
21
22
23 def find_ok(fields):
24 """find_ok helper function - finds field ending in "_ok"
25 """
26 for field_name in fields:
27 if field_name.endswith("_ok"):
28 return field_name
29 return None
30
31
32 def go_record(n, name):
33 r = Record([('go_i', n, DIR_FANIN),
34 ('rel_o', n, DIR_FANOUT)], name=name)
35 r.go_i.reset_less = True
36 r.rel_o.reset_less = True
37 return r
38
39
40 # see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
41
42 class CompUnitRecord(RegSpec, RecordObject):
43 """CompUnitRecord
44
45 base class for Computation Units, to provide a uniform API
46 and allow "record.connect" etc. to be used, particularly when
47 it comes to connecting multiple Computation Units up as a block
48 (very laborious)
49
50 LDSTCompUnitRecord should derive from this class and add the
51 additional signals it requires
52
53 :subkls: the class (not an instance) needed to construct the opcode
54 :rwid: either an integer (specifies width of all regs) or a "regspec"
55
56 see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
57 """
58
59 def __init__(self, subkls, rwid, n_src=None, n_dst=None, name=None):
60 RegSpec.__init__(self, rwid, n_src, n_dst)
61 print ("name", name)
62 RecordObject.__init__(self)
63 self._subkls = subkls
64 n_src, n_dst = self._n_src, self._n_dst
65
66 # create source operands
67 src = []
68 for i in range(n_src):
69 j = i + 1 # name numbering to match src1/src2
70 sname = "src%d_i" % j
71 rw = self._get_srcwid(i)
72 sreg = Signal(rw, name=sname, reset_less=True)
73 setattr(self, sname, sreg)
74 src.append(sreg)
75 self._src_i = src
76
77 # create dest operands
78 dst = []
79 for i in range(n_dst):
80 j = i + 1 # name numbering to match dest1/2...
81 dname = "dest%d_o" % j
82 rw = self._get_dstwid(i)
83 # dreg = Data(rw, name=name) XXX ??? output needs to be a Data type?
84 dreg = Signal(rw, name=dname, reset_less=True)
85 setattr(self, dname, dreg)
86 dst.append(dreg)
87 self._dest = dst
88
89 # operation / data input
90 self.oper_i = subkls(name="oper_i_%s" % name) # operand
91
92 # create read/write and other scoreboard signalling
93 self.rd = go_record(n_src, name="cu_rd") # read in, req out
94 self.wr = go_record(n_dst, name="cu_wr") # write in, req out
95 # read / write mask
96 self.rdmaskn = Signal(n_src, name="cu_rdmaskn_i", reset_less=True)
97 self.wrmask = Signal(n_dst, name="cu_wrmask_o", reset_less=True)
98
99 # fn issue in
100 self.issue_i = Signal(name="cu_issue_i", reset_less=True)
101 # shadow function, defaults to ON
102 self.shadown_i = Signal(name="cu_shadown_i", reset=1)
103 # go die (reset)
104 self.go_die_i = Signal(name="cu_go_die_i")
105
106 # output (busy/done)
107 self.busy_o = Signal(name="cu_busy_o", reset_less=True) # fn busy out
108 self.done_o = Signal(name="cu_done_o", reset_less=True)
109
110
111 class MultiCompUnit(RegSpecALUAPI, Elaboratable):
112 def __init__(self, rwid, alu, opsubsetkls, n_src=2, n_dst=1, name=None):
113 """MultiCompUnit
114
115 * :rwid: width of register latches (TODO: allocate per regspec)
116 * :alu: ALU (pipeline, FSM) - must conform to nmutil Pipe API
117 * :opsubsetkls: subset of Decode2ExecuteType
118 * :n_src: number of src operands
119 * :n_dst: number of destination operands
120 """
121 RegSpecALUAPI.__init__(self, rwid, alu)
122 self.alu_name = name or "alu"
123 self.opsubsetkls = opsubsetkls
124 self.cu = cu = CompUnitRecord(opsubsetkls, rwid, n_src, n_dst,
125 name=name)
126 n_src, n_dst = self.n_src, self.n_dst = cu._n_src, cu._n_dst
127 print("n_src %d n_dst %d" % (self.n_src, self.n_dst))
128
129 # convenience names for src operands
130 for i in range(n_src):
131 j = i + 1 # name numbering to match src1/src2
132 name = "src%d_i" % j
133 setattr(self, name, getattr(cu, name))
134
135 # convenience names for dest operands
136 for i in range(n_dst):
137 j = i + 1 # name numbering to match dest1/2...
138 name = "dest%d_o" % j
139 setattr(self, name, getattr(cu, name))
140
141 # more convenience names
142 self.rd = cu.rd
143 self.wr = cu.wr
144 self.rdmaskn = cu.rdmaskn
145 self.wrmask = cu.wrmask
146 self.go_rd_i = self.rd.go_i # temporary naming
147 self.go_wr_i = self.wr.go_i # temporary naming
148 self.rd_rel_o = self.rd.rel_o # temporary naming
149 self.req_rel_o = self.wr.rel_o # temporary naming
150 self.issue_i = cu.issue_i
151 self.shadown_i = cu.shadown_i
152 self.go_die_i = cu.go_die_i
153
154 # operation / data input
155 self.oper_i = cu.oper_i
156 self.src_i = cu._src_i
157
158 self.busy_o = cu.busy_o
159 self.dest = cu._dest
160 self.data_o = self.dest[0] # Dest out
161 self.done_o = cu.done_o
162
163 def _mux_op(self, m, sl, op_is_imm, imm, i):
164 # select imm if opcode says so. however also change the latch
165 # to trigger *from* the opcode latch instead.
166 src_or_imm = Signal(self.cu._get_srcwid(i), reset_less=True)
167 src_sel = Signal(reset_less=True)
168 m.d.comb += src_sel.eq(Mux(op_is_imm, self.opc_l.q, sl[i][2]))
169 m.d.comb += src_or_imm.eq(Mux(op_is_imm, imm, self.src_i[i]))
170 # overwrite 1st src-latch with immediate-muxed stuff
171 sl[i][0] = src_or_imm
172 sl[i][2] = src_sel
173 sl[i][3] = ~op_is_imm # change rd.rel[i] gate condition
174
175 def elaborate(self, platform):
176 m = Module()
177 setattr(m.submodules, self.alu_name, self.alu)
178 m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
179 m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
180 m.submodules.req_l = req_l = SRLatch(False, self.n_dst, name="req")
181 m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
182 m.submodules.rok_l = rok_l = SRLatch(sync=False, name="rdok")
183 self.opc_l, self.src_l = opc_l, src_l
184
185 # ALU only proceeds when all src are ready. rd_rel_o is delayed
186 # so combine it with go_rd_i. if all bits are set we're good
187 all_rd = Signal(reset_less=True)
188 m.d.comb += all_rd.eq(self.busy_o & rok_l.q &
189 (((~self.rd.rel_o) | self.rd.go_i).all()))
190
191 # generate read-done pulse
192 all_rd_pulse = Signal(reset_less=True)
193 m.d.comb += all_rd_pulse.eq(rising_edge(m, all_rd))
194
195 # create rising pulse from alu valid condition.
196 alu_done = Signal(reset_less=True)
197 alu_pulse = Signal(reset_less=True)
198 alu_pulsem = Signal(self.n_dst, reset_less=True)
199 m.d.comb += alu_done.eq(self.alu.n.valid_o)
200 m.d.comb += alu_pulse.eq(rising_edge(m, alu_done))
201 m.d.comb += alu_pulsem.eq(Repl(alu_pulse, self.n_dst))
202
203 # sigh bug where req_l gets both set and reset raised at same time
204 prev_wr_go = Signal(self.n_dst)
205 brd = Repl(self.busy_o, self.n_dst)
206 m.d.sync += prev_wr_go.eq(self.wr.go_i & brd)
207
208 # write_requests all done
209 # req_done works because any one of the last of the writes
210 # is enough, when combined with when read-phase is done (rst_l.q)
211 wr_any = Signal(reset_less=True)
212 req_done = Signal(reset_less=True)
213 m.d.comb += self.done_o.eq(self.busy_o &
214 ~((self.wr.rel_o & ~self.wrmask).bool()))
215 m.d.comb += wr_any.eq(self.wr.go_i.bool() | prev_wr_go.bool())
216 m.d.comb += req_done.eq(wr_any & ~self.alu.n.ready_i &
217 ((req_l.q & self.wrmask) == 0))
218 # argh, complicated hack: if there are no regs to write,
219 # instead of waiting for regs that are never going to happen,
220 # we indicate "done" when the ALU is "done"
221 with m.If((self.wrmask == 0) &
222 self.alu.n.ready_i & self.alu.n.valid_o & self.busy_o):
223 m.d.comb += req_done.eq(1)
224
225 # shadow/go_die
226 reset = Signal(reset_less=True)
227 rst_r = Signal(reset_less=True) # reset latch off
228 reset_w = Signal(self.n_dst, reset_less=True)
229 reset_r = Signal(self.n_src, reset_less=True)
230 m.d.comb += reset.eq(req_done | self.go_die_i)
231 m.d.comb += rst_r.eq(self.issue_i | self.go_die_i)
232 m.d.comb += reset_w.eq(self.wr.go_i | Repl(self.go_die_i, self.n_dst))
233 m.d.comb += reset_r.eq(self.rd.go_i | Repl(self.go_die_i, self.n_src))
234
235 # read-done,wr-proceed latch
236 m.d.sync += rok_l.s.eq(self.issue_i) # set up when issue starts
237 m.d.sync += rok_l.r.eq(self.alu.n.valid_o & self.busy_o) # ALU done
238
239 # wr-done, back-to-start latch
240 m.d.sync += rst_l.s.eq(all_rd) # set when read-phase is fully done
241 m.d.sync += rst_l.r.eq(rst_r) # *off* on issue
242
243 # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
244 m.d.sync += opc_l.s.eq(self.issue_i) # set on issue
245 m.d.sync += opc_l.r.eq(req_done) # reset on ALU
246
247 # src operand latch (not using go_wr_i)
248 m.d.sync += src_l.s.eq(Repl(self.issue_i, self.n_src))
249 m.d.sync += src_l.r.eq(reset_r)
250
251 # dest operand latch (not using issue_i)
252 m.d.sync += req_l.s.eq(alu_pulsem & self.wrmask)
253 m.d.sync += req_l.r.eq(reset_w | prev_wr_go)
254
255 # pass operation to the ALU (sync: plenty time to wait for src reads)
256 op = self.get_op()
257 with m.If(self.issue_i):
258 m.d.sync += op.eq(self.oper_i)
259
260 # and for each output from the ALU: capture when ALU output is valid
261 drl = []
262 wrok = []
263 for i in range(self.n_dst):
264 name = "data_r%d" % i
265 lro = self.get_out(i)
266 ok = Const(1, 1)
267 if isinstance(lro, Record):
268 data_r = Record.like(lro, name=name)
269 print("wr fields", i, lro, data_r.fields)
270 # bye-bye abstract interface design..
271 fname = find_ok(data_r.fields)
272 if fname:
273 ok = getattr(lro, fname)
274 else:
275 data_r = Signal.like(lro, name=name, reset_less=True)
276 wrok.append(ok & self.busy_o)
277 with m.If(alu_pulse):
278 m.d.sync += data_r.eq(lro)
279 with m.If(self.issue_i):
280 m.d.sync += data_r.eq(0)
281 drl.append(data_r)
282
283 # ok, above we collated anything with an "ok" on the output side
284 # now actually use those to create a write-mask. this basically
285 # is now the Function Unit API tells the Comp Unit "do not request
286 # a regfile port because this particular output is not valid"
287 m.d.comb += self.wrmask.eq(Cat(*wrok))
288
289 # create list of src/alu-src/src-latch. override 1st and 2nd one below.
290 # in the case, for ALU and Logical pipelines, we assume RB is the
291 # 2nd operand in the input "regspec". see for example
292 # soc.fu.alu.pipe_data.ALUInputData
293 sl = []
294 print("src_i", self.src_i)
295 for i in range(self.n_src):
296 sl.append([self.src_i[i], self.get_in(i), src_l.q[i], Const(1, 1)])
297
298 # if the operand subset has "zero_a" we implicitly assume that means
299 # src_i[0] is an INT reg type where zero can be multiplexed in, instead.
300 # see https://bugs.libre-soc.org/show_bug.cgi?id=336
301 if hasattr(op, "zero_a"):
302 # select zero imm if opcode says so. however also change the latch
303 # to trigger *from* the opcode latch instead.
304 self._mux_op(m, sl, op.zero_a, 0, 0)
305
306 # if the operand subset has "imm_data" we implicitly assume that means
307 # "this is an INT ALU/Logical FU jobbie, RB is muxed with the immediate"
308 if hasattr(op, "imm_data"):
309 # select immediate if opcode says so. however also change the latch
310 # to trigger *from* the opcode latch instead.
311 op_is_imm = op.imm_data.ok
312 imm = op.imm_data.data
313 self._mux_op(m, sl, op_is_imm, imm, 1)
314
315 # create a latch/register for src1/src2 (even if it is a copy of imm)
316 for i in range(self.n_src):
317 src, alusrc, latch, _ = sl[i]
318 latchregister(m, src, alusrc, latch, name="src_r%d" % i)
319
320 # -----
321 # ALU connection / interaction
322 # -----
323
324 # on a go_read, tell the ALU we're accepting data.
325 m.submodules.alui_l = alui_l = SRLatch(False, name="alui")
326 m.d.comb += self.alu.p.valid_i.eq(alui_l.q)
327 m.d.sync += alui_l.r.eq(self.alu.p.ready_o & alui_l.q)
328 m.d.comb += alui_l.s.eq(all_rd_pulse)
329
330 # ALU output "ready" side. alu "ready" indication stays hi until
331 # ALU says "valid".
332 m.submodules.alu_l = alu_l = SRLatch(False, name="alu")
333 m.d.comb += self.alu.n.ready_i.eq(alu_l.q)
334 m.d.sync += alu_l.r.eq(self.alu.n.valid_o & alu_l.q)
335 m.d.comb += alu_l.s.eq(all_rd_pulse)
336
337 # -----
338 # outputs
339 # -----
340
341 slg = Cat(*map(lambda x: x[3], sl)) # get req gate conditions
342 # all request signals gated by busy_o. prevents picker problems
343 m.d.comb += self.busy_o.eq(opc_l.q) # busy out
344
345 # read-release gated by busy (and read-mask)
346 bro = Repl(self.busy_o, self.n_src)
347 m.d.comb += self.rd.rel_o.eq(src_l.q & bro & slg & ~self.rdmaskn)
348
349 # write-release gated by busy and by shadow (and write-mask)
350 brd = Repl(self.busy_o & self.shadown_i, self.n_dst)
351 m.d.comb += self.wr.rel_o.eq(req_l.q & brd & self.wrmask)
352
353 # output the data from the latch on go_write
354 for i in range(self.n_dst):
355 with m.If(self.wr.go_i[i] & self.busy_o):
356 m.d.comb += self.dest[i].eq(drl[i])
357
358 return m
359
360 def get_fu_out(self, i):
361 return self.dest[i]
362
363 def __iter__(self):
364 yield self.rd.go_i
365 yield self.wr.go_i
366 yield self.issue_i
367 yield self.shadown_i
368 yield self.go_die_i
369 yield from self.oper_i.ports()
370 yield self.src1_i
371 yield self.src2_i
372 yield self.busy_o
373 yield self.rd.rel_o
374 yield self.wr.rel_o
375 yield self.data_o
376
377 def ports(self):
378 return list(self)