Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / experiment / compldst_multi.py
1 """LOAD / STORE Computation Unit.
2
3 This module covers POWER9-compliant Load and Store operations,
4 with selection on each between immediate and indexed mode as
5 options for the calculation of the Effective Address (EA),
6 and also "update" mode which optionally stores that EA into
7 an additional register.
8
9 ----
10 Note: it took 15 attempts over several weeks to redraw the diagram
11 needed to capture this FSM properly. To understand it fully, please
12 take the time to review the links, video, and diagram.
13 ----
14
15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
16 compute the "Effective Address", and, when ready the operand (src3_i)
17 is stored in the computed address (passed through to the PortInterface)
18
19 Loads are activated when Go_Write[0] is enabled. The EA is computed,
20 and (as long as there was no exception) the data comes out (at any
21 time from the PortInterface), and is captured by the LDCompSTUnit.
22
23 Both LD and ST may request that the address be computed from summing
24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
25 the immediate (from the opcode).
26
27 Both LD and ST may also request "update" mode (op_is_update) which
28 activates the use of Go_Write[1] to control storage of the EA into
29 a *second* operand in the register file.
30
31 Thus this module has *TWO* write-requests to the register file and
32 *THREE* read-requests to the register file (not all at the same time!)
33 The regfile port usage is:
34
35 * LD-imm 1R1W
36 * LD-imm-update 1R2W
37 * LD-idx 2R1W
38 * LD-idx-update 2R2W
39
40 * ST-imm 2R
41 * ST-imm-update 2R1W
42 * ST-idx 3R
43 * ST-idx-update 3R1W
44
45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
47 the nested FSMs below are *combinatorial*).
48
49 * One FSM covers Operand collection and communication address-side
50 with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
51
52 * A second FSM activates to cover LD. it activates if op_is_ld is true
53
54 * A third FSM activates to cover ST. it activates if op_is_st is true
55
56 * The "overall" (fourth) FSM coordinates the progression and completion
57 of the three other FSMs, firing "WR_RESET" which switches off "busy"
58
59 Full diagram:
60
61 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
62
63 Links including to walk-through videos:
64
65 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
66 * http://libre-soc.org/openpower/isa/fixedload
67 * http://libre-soc.org/openpower/isa/fixedstore
68
69 Related Bugreports:
70
71 * https://bugs.libre-soc.org/show_bug.cgi?id=302
72 * https://bugs.libre-soc.org/show_bug.cgi?id=216
73
74 Terminology:
75
76 * EA - Effective Address
77 * LD - Load
78 * ST - Store
79 """
80
81 from nmigen.compat.sim import run_simulation
82 from nmigen.cli import verilog, rtlil
83 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
84 from nmigen.hdl.rec import Record, Layout
85
86 from nmutil.latch import SRLatch, latchregister
87 from nmutil.byterev import byte_reverse
88 from nmutil.extend import exts
89
90 from soc.experiment.compalu_multi import go_record, CompUnitRecord
91 from soc.experiment.l0_cache import PortInterface
92 from soc.experiment.pimem import LDSTException
93 from soc.fu.regspec import RegSpecAPI
94
95 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
96 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
97 from openpower.decoder.power_decoder2 import Data
98
99
100 class LDSTCompUnitRecord(CompUnitRecord):
101 def __init__(self, rwid, opsubset=CompLDSTOpSubset, name=None):
102 CompUnitRecord.__init__(self, opsubset, rwid,
103 n_src=3, n_dst=2, name=name)
104
105 self.ad = go_record(1, name="cu_ad") # address go in, req out
106 self.st = go_record(1, name="cu_st") # store go in, req out
107
108 self.exception_o = LDSTException("exc")
109
110 self.ld_o = Signal(reset_less=True) # operation is a LD
111 self.st_o = Signal(reset_less=True) # operation is a ST
112
113 # hmm... are these necessary?
114 self.load_mem_o = Signal(reset_less=True) # activate memory LOAD
115 self.stwd_mem_o = Signal(reset_less=True) # activate memory STORE
116
117
118 class LDSTCompUnit(RegSpecAPI, Elaboratable):
119 """LOAD / STORE Computation Unit
120
121 Inputs
122 ------
123
124 * :pi: a PortInterface to the memory subsystem (read-write capable)
125 * :rwid: register width
126 * :awid: address width
127
128 Data inputs
129 -----------
130 * :src_i: Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
131
132 Data (outputs)
133 --------------
134 * :data_o: Dest out (LD) - managed by wr[0] go/req
135 * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
136 * :exception_o: Address/Data Exception occurred. LD/ST must terminate
137
138 TODO: make exception_o a data-type rather than a single-bit signal
139 (see bug #302)
140
141 Control Signals (In)
142 --------------------
143
144 * :oper_i: operation being carried out (POWER9 decode LD/ST subset)
145 * :issue_i: LD/ST is being "issued".
146 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
147 * :go_rd_i: read is being actioned (latches in src regs)
148 * :go_wr_i: write mode (exactly like ALU CompUnit)
149 * :go_ad_i: address is being actioned (triggers actual mem LD)
150 * :go_st_i: store is being actioned (triggers actual mem STORE)
151 * :go_die_i: resets the unit back to "wait for issue"
152
153 Control Signals (Out)
154 ---------------------
155
156 * :busy_o: function unit is busy
157 * :rd_rel_o: request src1/src2
158 * :adr_rel_o: request address (from mem)
159 * :sto_rel_o: request store (to mem)
160 * :req_rel_o: request write (result)
161 * :load_mem_o: activate memory LOAD
162 * :stwd_mem_o: activate memory STORE
163
164 Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
165 in a single cycle and the CompUnit set back to doing another op.
166 This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
167 depending on whether the operation is a ST or LD.
168
169 Note: LDSTCompUnit takes care of LE/BE normalisation:
170 * LD data is normalised after receipt from the PortInterface
171 * ST data is normalised *prior* to sending onto the PortInterface
172 TODO: use one module for the byte-reverse as it's quite expensive in gates
173 """
174
175 def __init__(self, pi=None, rwid=64, awid=48, opsubset=CompLDSTOpSubset,
176 debugtest=False, name=None):
177 super().__init__(rwid)
178 self.awid = awid
179 self.pi = pi
180 self.cu = cu = LDSTCompUnitRecord(rwid, opsubset, name=name)
181 self.debugtest = debugtest
182
183 # POWER-compliant LD/ST has index and update: *fixed* number of ports
184 self.n_src = n_src = 3 # RA, RB, RT/RS
185 self.n_dst = n_dst = 2 # RA, RT/RS
186
187 # set up array of src and dest signals
188 for i in range(n_src):
189 j = i + 1 # name numbering to match src1/src2
190 name = "src%d_i" % j
191 setattr(self, name, getattr(cu, name))
192
193 dst = []
194 for i in range(n_dst):
195 j = i + 1 # name numbering to match dest1/2...
196 name = "dest%d_o" % j
197 setattr(self, name, getattr(cu, name))
198
199 # convenience names
200 self.rd = cu.rd
201 self.wr = cu.wr
202 self.rdmaskn = cu.rdmaskn
203 self.wrmask = cu.wrmask
204 self.ad = cu.ad
205 self.st = cu.st
206 self.dest = cu._dest
207
208 # HACK: get data width from dest[0]. this is used across the board
209 # (it really shouldn't be)
210 self.data_wid = self.dest[0].shape()
211
212 self.go_rd_i = self.rd.go_i # temporary naming
213 self.go_wr_i = self.wr.go_i # temporary naming
214 self.go_ad_i = self.ad.go_i # temp naming: go address in
215 self.go_st_i = self.st.go_i # temp naming: go store in
216
217 self.rd_rel_o = self.rd.rel_o # temporary naming
218 self.req_rel_o = self.wr.rel_o # temporary naming
219 self.adr_rel_o = self.ad.rel_o # request address (from mem)
220 self.sto_rel_o = self.st.rel_o # request store (to mem)
221
222 self.issue_i = cu.issue_i
223 self.shadown_i = cu.shadown_i
224 self.go_die_i = cu.go_die_i
225
226 self.oper_i = cu.oper_i
227 self.src_i = cu._src_i
228
229 self.data_o = Data(self.data_wid, name="o") # Dest1 out: RT
230 self.addr_o = Data(self.data_wid, name="ea") # Addr out: Update => RA
231 self.exception_o = cu.exception_o
232 self.done_o = cu.done_o
233 self.busy_o = cu.busy_o
234
235 self.ld_o = cu.ld_o
236 self.st_o = cu.st_o
237
238 self.load_mem_o = cu.load_mem_o
239 self.stwd_mem_o = cu.stwd_mem_o
240
241 def elaborate(self, platform):
242 m = Module()
243
244 # temp/convenience
245 comb = m.d.comb
246 sync = m.d.sync
247 issue_i = self.issue_i
248
249 #####################
250 # latches for the FSM.
251 m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
252 m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
253 m.submodules.alu_l = alu_l = SRLatch(sync=False, name="alu")
254 m.submodules.adr_l = adr_l = SRLatch(sync=False, name="adr")
255 m.submodules.lod_l = lod_l = SRLatch(sync=False, name="lod")
256 m.submodules.sto_l = sto_l = SRLatch(sync=False, name="sto")
257 m.submodules.wri_l = wri_l = SRLatch(sync=False, name="wri")
258 m.submodules.upd_l = upd_l = SRLatch(sync=False, name="upd")
259 m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
260 m.submodules.lsd_l = lsd_l = SRLatch(sync=False, name="lsd") # done
261
262 ####################
263 # signals
264
265 # opcode decode
266 op_is_ld = Signal(reset_less=True)
267 op_is_st = Signal(reset_less=True)
268
269 # ALU/LD data output control
270 alu_valid = Signal(reset_less=True) # ALU operands are valid
271 alu_ok = Signal(reset_less=True) # ALU out ok (1 clock delay valid)
272 addr_ok = Signal(reset_less=True) # addr ok (from PortInterface)
273 ld_ok = Signal(reset_less=True) # LD out ok from PortInterface
274 wr_any = Signal(reset_less=True) # any write (incl. store)
275 rda_any = Signal(reset_less=True) # any read for address ops
276 rd_done = Signal(reset_less=True) # all *necessary* operands read
277 wr_reset = Signal(reset_less=True) # final reset condition
278
279 # LD and ALU out
280 alu_o = Signal(self.data_wid, reset_less=True)
281 ldd_o = Signal(self.data_wid, reset_less=True)
282
283 ##############################
284 # reset conditions for latches
285
286 # temporaries (also convenient when debugging)
287 reset_o = Signal(reset_less=True) # reset opcode
288 reset_w = Signal(reset_less=True) # reset write
289 reset_u = Signal(reset_less=True) # reset update
290 reset_a = Signal(reset_less=True) # reset adr latch
291 reset_i = Signal(reset_less=True) # issue|die (use a lot)
292 reset_r = Signal(self.n_src, reset_less=True) # reset src
293 reset_s = Signal(reset_less=True) # reset store
294
295 comb += reset_i.eq(issue_i | self.go_die_i) # various
296 comb += reset_o.eq(self.done_o | self.go_die_i) # opcode reset
297 comb += reset_w.eq(self.wr.go_i[0] | self.go_die_i) # write reg 1
298 comb += reset_u.eq(self.wr.go_i[1] | self.go_die_i) # update (reg 2)
299 comb += reset_s.eq(self.go_st_i | self.go_die_i) # store reset
300 comb += reset_r.eq(self.rd.go_i | Repl(self.go_die_i, self.n_src))
301 comb += reset_a.eq(self.go_ad_i | self.go_die_i)
302
303 p_st_go = Signal(reset_less=True)
304 sync += p_st_go.eq(self.st.go_i)
305
306 # decode bits of operand (latched)
307 oper_r = CompLDSTOpSubset(name="oper_r") # Dest register
308 comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE) # ST
309 comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD) # LD
310 op_is_update = oper_r.ldst_mode == LDSTMode.update # UPDATE
311 op_is_cix = oper_r.ldst_mode == LDSTMode.cix # cache-inhibit
312 comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
313 comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
314 comb += self.ld_o.eq(op_is_ld)
315 comb += self.st_o.eq(op_is_st)
316
317 ##########################
318 # FSM implemented through sequence of latches. approximately this:
319 # - opc_l : opcode
320 # - src_l[0] : operands
321 # - src_l[1]
322 # - alu_l : looks after add of src1/2/imm (EA)
323 # - adr_l : waits for add (EA)
324 # - upd_l : waits for adr and Regfile (port 2)
325 # - src_l[2] : ST
326 # - lod_l : waits for adr (EA) and for LD Data
327 # - wri_l : waits for LD Data and Regfile (port 1)
328 # - st_l : waits for alu and operand2
329 # - rst_l : waits for all FSM paths to converge.
330 # NOTE: use sync to stop combinatorial loops.
331
332 # opcode latch - inverted so that busy resets to 0
333 # note this MUST be sync so as to avoid a combinatorial loop
334 # between busy_o and issue_i on the reset latch (rst_l)
335 sync += opc_l.s.eq(issue_i) # XXX NOTE: INVERTED FROM book!
336 sync += opc_l.r.eq(reset_o) # XXX NOTE: INVERTED FROM book!
337
338 # src operand latch
339 sync += src_l.s.eq(Repl(issue_i, self.n_src))
340 sync += src_l.r.eq(reset_r)
341
342 # alu latch. use sync-delay between alu_ok and valid to generate pulse
343 comb += alu_l.s.eq(reset_i)
344 comb += alu_l.r.eq(alu_ok & ~alu_valid & ~rda_any)
345
346 # addr latch
347 comb += adr_l.s.eq(reset_i)
348 sync += adr_l.r.eq(reset_a)
349
350 # ld latch
351 comb += lod_l.s.eq(reset_i)
352 comb += lod_l.r.eq(ld_ok)
353
354 # dest operand latch
355 comb += wri_l.s.eq(issue_i)
356 sync += wri_l.r.eq(reset_w | Repl(wr_reset |
357 (~self.pi.busy_o & op_is_update),
358 #(self.pi.busy_o & op_is_update),
359 #self.done_o | (self.pi.busy_o & op_is_update),
360 self.n_dst))
361
362 # update-mode operand latch (EA written to reg 2)
363 sync += upd_l.s.eq(reset_i)
364 sync += upd_l.r.eq(reset_u)
365
366 # store latch
367 comb += sto_l.s.eq(addr_ok & op_is_st)
368 sync += sto_l.r.eq(reset_s | p_st_go)
369
370 # ld/st done. needed to stop LD/ST from activating repeatedly
371 comb += lsd_l.s.eq(issue_i)
372 sync += lsd_l.r.eq(reset_s | p_st_go | ld_ok)
373
374 # reset latch
375 comb += rst_l.s.eq(addr_ok) # start when address is ready
376 comb += rst_l.r.eq(issue_i)
377
378 # create a latch/register for the operand
379 with m.If(self.issue_i):
380 sync += oper_r.eq(self.oper_i)
381 with m.If(self.done_o):
382 sync += oper_r.eq(0)
383
384 # and for LD
385 ldd_r = Signal(self.data_wid, reset_less=True) # Dest register
386 latchregister(m, ldd_o, ldd_r, ld_ok, name="ldo_r")
387
388 # and for each input from the incoming src operands
389 srl = []
390 for i in range(self.n_src):
391 name = "src_r%d" % i
392 src_r = Signal(self.data_wid, name=name, reset_less=True)
393 with m.If(self.rd.go_i[i]):
394 sync += src_r.eq(self.src_i[i])
395 with m.If(self.issue_i):
396 sync += src_r.eq(0)
397 srl.append(src_r)
398
399 # and one for the output from the ADD (for the EA)
400 addr_r = Signal(self.data_wid, reset_less=True) # Effective Address
401 latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
402
403 # select either zero or src1 if opcode says so
404 op_is_z = oper_r.zero_a
405 src1_or_z = Signal(self.data_wid, reset_less=True)
406 m.d.comb += src1_or_z.eq(Mux(op_is_z, 0, srl[0]))
407
408 # select either immediate or src2 if opcode says so
409 op_is_imm = oper_r.imm_data.ok
410 src2_or_imm = Signal(self.data_wid, reset_less=True)
411 m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.data, srl[1]))
412
413 # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
414 comb += alu_o.eq(src1_or_z + src2_or_imm) # actual EA
415 m.d.sync += alu_ok.eq(alu_valid) # keep ack in sync with EA
416
417 ############################
418 # Control Signal calculation
419
420 # busy signal
421 busy_o = self.busy_o
422 comb += self.busy_o.eq(opc_l.q) # | self.pi.busy_o) # busy out
423
424 # 1st operand read-request only when zero not active
425 # 2nd operand only needed when immediate is not active
426 slg = Cat(op_is_z, op_is_imm)
427 bro = Repl(self.busy_o, self.n_src)
428 comb += self.rd.rel_o.eq(src_l.q & bro & ~slg & ~self.rdmaskn)
429
430 # note when the address-related read "go" signals are active
431 comb += rda_any.eq(self.rd.go_i[0] | self.rd.go_i[1])
432
433 # alu input valid when 1st and 2nd ops done (or imm not active)
434 comb += alu_valid.eq(busy_o & ~(self.rd.rel_o[0] | self.rd.rel_o[1]))
435
436 # 3rd operand only needed when operation is a store
437 comb += self.rd.rel_o[2].eq(src_l.q[2] & busy_o & op_is_st)
438
439 # all reads done when alu is valid and 3rd operand needed
440 comb += rd_done.eq(alu_valid & ~self.rd.rel_o[2])
441
442 # address release only if addr ready, but Port must be idle
443 comb += self.adr_rel_o.eq(alu_valid & adr_l.q & busy_o)
444
445 # store release when st ready *and* all operands read (and no shadow)
446 comb += self.st.rel_o.eq(sto_l.q & busy_o & rd_done & op_is_st &
447 self.shadown_i)
448
449 # request write of LD result. waits until shadow is dropped.
450 comb += self.wr.rel_o[0].eq(rd_done & wri_l.q & busy_o & lod_l.qn &
451 op_is_ld & self.shadown_i)
452
453 # request write of EA result only in update mode
454 comb += self.wr.rel_o[1].eq(upd_l.q & busy_o & op_is_update &
455 alu_valid & self.shadown_i)
456
457 # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
458 comb += wr_any.eq(self.st.go_i | p_st_go |
459 self.wr.go_i[0] | self.wr.go_i[1])
460 comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
461 ~(self.st.rel_o | self.wr.rel_o[0] |
462 self.wr.rel_o[1]) &
463 (lod_l.qn | op_is_st)
464 )
465 comb += self.done_o.eq(wr_reset & (~self.pi.busy_o | op_is_ld))
466
467 ######################
468 # Data/Address outputs
469
470 # put the LD-output register directly onto the output bus on a go_write
471 comb += self.data_o.data.eq(self.dest[0])
472 with m.If(self.wr.go_i[0]):
473 comb += self.dest[0].eq(ldd_r)
474
475 # "update" mode, put address out on 2nd go-write
476 comb += self.addr_o.data.eq(self.dest[1])
477 with m.If(op_is_update & self.wr.go_i[1]):
478 comb += self.dest[1].eq(addr_r)
479
480 # need to look like MultiCompUnit: put wrmask out.
481 # XXX may need to make this enable only when write active
482 comb += self.wrmask.eq(bro & Cat(op_is_ld, op_is_update))
483
484 ###########################
485 # PortInterface connections
486 pi = self.pi
487
488 # connect to LD/ST PortInterface.
489 comb += pi.is_ld_i.eq(op_is_ld & busy_o) # decoded-LD
490 comb += pi.is_st_i.eq(op_is_st & busy_o) # decoded-ST
491 comb += pi.data_len.eq(oper_r.data_len) # data_len
492 # address: use sync to avoid long latency
493 sync += pi.addr.data.eq(addr_r) # EA from adder
494 sync += pi.addr.ok.eq(alu_ok & lsd_l.q) # "do address stuff" (once)
495 comb += self.exception_o.eq(pi.exception_o) # exception occurred
496 comb += addr_ok.eq(self.pi.addr_ok_o) # no exc, address fine
497
498 # byte-reverse on LD
499 revnorev = Signal(64, reset_less=True)
500 with m.If(oper_r.byte_reverse):
501 # byte-reverse the data based on ld/st width (turn it to LE)
502 data_len = oper_r.data_len
503 lddata_r = byte_reverse(m, 'lddata_r', pi.ld.data, data_len)
504 comb += revnorev.eq(lddata_r) # put reversed- data out
505 with m.Else():
506 comb += revnorev.eq(pi.ld.data) # put data out, straight (as BE)
507
508 # then check sign-extend
509 with m.If(oper_r.sign_extend):
510 # okok really should "if data_len == 4" and so on here
511 with m.If(oper_r.data_len == 2):
512 comb += ldd_o.eq(exts(revnorev, 16, 64)) # sign-extend hword
513 with m.Else():
514 comb += ldd_o.eq(exts(revnorev, 32, 64)) # sign-extend dword
515 with m.Else():
516 comb += ldd_o.eq(revnorev)
517
518 # ld - ld gets latched in via lod_l
519 comb += ld_ok.eq(pi.ld.ok) # ld.ok *closes* (freezes) ld data
520
521 # byte-reverse on ST
522 op3 = srl[2] # 3rd operand latch
523 with m.If(oper_r.byte_reverse):
524 # byte-reverse the data based on width
525 data_len = oper_r.data_len
526 stdata_r = byte_reverse(m, 'stdata_r', op3, data_len)
527 comb += pi.st.data.eq(stdata_r)
528 with m.Else():
529 comb += pi.st.data.eq(op3)
530 # store - data goes in based on go_st
531 comb += pi.st.ok.eq(self.st.go_i) # go store signals st data valid
532
533 return m
534
535 def get_out(self, i):
536 """make LDSTCompUnit look like RegSpecALUAPI"""
537 if i == 0:
538 return self.data_o
539 if i == 1:
540 return self.addr_o
541 # return self.dest[i]
542
543 def get_fu_out(self, i):
544 return self.get_out(i)
545
546 def __iter__(self):
547 yield self.rd.go_i
548 yield self.go_ad_i
549 yield self.wr.go_i
550 yield self.go_st_i
551 yield self.issue_i
552 yield self.shadown_i
553 yield self.go_die_i
554 yield from self.oper_i.ports()
555 yield from self.src_i
556 yield self.busy_o
557 yield self.rd.rel_o
558 yield self.adr_rel_o
559 yield self.sto_rel_o
560 yield self.wr.rel_o
561 yield from self.data_o.ports()
562 yield from self.addr_o.ports()
563 yield self.load_mem_o
564 yield self.stwd_mem_o
565
566 def ports(self):
567 return list(self)
568
569
570 def wait_for(sig, wait=True, test1st=False):
571 v = (yield sig)
572 print("wait for", sig, v, wait, test1st)
573 if test1st and bool(v) == wait:
574 return
575 while True:
576 yield
577 v = (yield sig)
578 #print("...wait for", sig, v)
579 if bool(v) == wait:
580 break
581
582
583 def store(dut, src1, src2, src3, imm, imm_ok=True, update=False,
584 byterev=True):
585 print("ST", src1, src2, src3, imm, imm_ok, update)
586 yield dut.oper_i.insn_type.eq(MicrOp.OP_STORE)
587 yield dut.oper_i.data_len.eq(2) # half-word
588 yield dut.oper_i.byte_reverse.eq(byterev)
589 yield dut.src1_i.eq(src1)
590 yield dut.src2_i.eq(src2)
591 yield dut.src3_i.eq(src3)
592 yield dut.oper_i.imm_data.imm.eq(imm)
593 yield dut.oper_i.imm_data.ok.eq(imm_ok)
594 yield dut.oper_i.update.eq(update)
595 yield dut.issue_i.eq(1)
596 yield
597 yield dut.issue_i.eq(0)
598
599 if imm_ok:
600 active_rel = 0b101
601 else:
602 active_rel = 0b111
603 # wait for all active rel signals to come up
604 while True:
605 rel = yield dut.rd.rel_o
606 if rel == active_rel:
607 break
608 yield
609 yield dut.rd.go.eq(active_rel)
610 yield
611 yield dut.rd.go.eq(0)
612
613 yield from wait_for(dut.adr_rel_o, False, test1st=True)
614 # yield from wait_for(dut.adr_rel_o)
615 # yield dut.ad.go.eq(1)
616 # yield
617 # yield dut.ad.go.eq(0)
618
619 if update:
620 yield from wait_for(dut.wr.rel_o[1])
621 yield dut.wr.go.eq(0b10)
622 yield
623 addr = yield dut.addr_o
624 print("addr", addr)
625 yield dut.wr.go.eq(0)
626 else:
627 addr = None
628
629 yield from wait_for(dut.sto_rel_o)
630 yield dut.go_st_i.eq(1)
631 yield
632 yield dut.go_st_i.eq(0)
633 yield from wait_for(dut.busy_o, False)
634 # wait_for(dut.stwd_mem_o)
635 yield
636 return addr
637
638
639 def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False,
640 byterev=True):
641 print("LD", src1, src2, imm, imm_ok, update)
642 yield dut.oper_i.insn_type.eq(MicrOp.OP_LOAD)
643 yield dut.oper_i.data_len.eq(2) # half-word
644 yield dut.oper_i.byte_reverse.eq(byterev)
645 yield dut.src1_i.eq(src1)
646 yield dut.src2_i.eq(src2)
647 yield dut.oper_i.zero_a.eq(zero_a)
648 yield dut.oper_i.imm_data.imm.eq(imm)
649 yield dut.oper_i.imm_data.ok.eq(imm_ok)
650 yield dut.issue_i.eq(1)
651 yield
652 yield dut.issue_i.eq(0)
653 yield
654
655 # set up read-operand flags
656 rd = 0b00
657 if not imm_ok: # no immediate means RB register needs to be read
658 rd |= 0b10
659 if not zero_a: # no zero-a means RA needs to be read
660 rd |= 0b01
661
662 # wait for the operands (RA, RB, or both)
663 if rd:
664 yield dut.rd.go.eq(rd)
665 yield from wait_for(dut.rd.rel_o)
666 yield dut.rd.go.eq(0)
667
668 yield from wait_for(dut.adr_rel_o, False, test1st=True)
669 # yield dut.ad.go.eq(1)
670 # yield
671 # yield dut.ad.go.eq(0)
672
673 if update:
674 yield from wait_for(dut.wr.rel_o[1])
675 yield dut.wr.go.eq(0b10)
676 yield
677 addr = yield dut.addr_o
678 print("addr", addr)
679 yield dut.wr.go.eq(0)
680 else:
681 addr = None
682
683 yield from wait_for(dut.wr.rel_o[0], test1st=True)
684 yield dut.wr.go.eq(1)
685 yield
686 data = yield dut.data_o
687 print(data)
688 yield dut.wr.go.eq(0)
689 yield from wait_for(dut.busy_o)
690 yield
691 # wait_for(dut.stwd_mem_o)
692 return data, addr
693
694
695 def ldst_sim(dut):
696
697 ###################
698 # immediate version
699
700 # two STs (different addresses)
701 yield from store(dut, 4, 0, 3, 2) # ST reg4 into addr rfile[reg3]+2
702 yield from store(dut, 2, 0, 9, 2) # ST reg4 into addr rfile[reg9]+2
703 yield
704 # two LDs (deliberately LD from the 1st address then 2nd)
705 data, addr = yield from load(dut, 4, 0, 2)
706 assert data == 0x0003, "returned %x" % data
707 data, addr = yield from load(dut, 2, 0, 2)
708 assert data == 0x0009, "returned %x" % data
709 yield
710
711 # indexed version
712 yield from store(dut, 9, 5, 3, 0, imm_ok=False)
713 data, addr = yield from load(dut, 9, 5, 0, imm_ok=False)
714 assert data == 0x0003, "returned %x" % data
715
716 # update-immediate version
717 addr = yield from store(dut, 9, 6, 3, 2, update=True)
718 assert addr == 0x000b, "returned %x" % addr
719
720 # update-indexed version
721 data, addr = yield from load(dut, 9, 5, 0, imm_ok=False, update=True)
722 assert data == 0x0003, "returned %x" % data
723 assert addr == 0x000e, "returned %x" % addr
724
725 # immediate *and* zero version
726 data, addr = yield from load(dut, 1, 4, 8, imm_ok=True, zero_a=True)
727 assert data == 0x0008, "returned %x" % data
728
729
730 class TestLDSTCompUnit(LDSTCompUnit):
731
732 def __init__(self, rwid):
733 from soc.experiment.l0_cache import TstL0CacheBuffer
734 self.l0 = l0 = TstL0CacheBuffer()
735 pi = l0.l0.dports[0].pi
736 LDSTCompUnit.__init__(self, pi, rwid, 4)
737
738 def elaborate(self, platform):
739 m = LDSTCompUnit.elaborate(self, platform)
740 m.submodules.l0 = self.l0
741 m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
742 return m
743
744
745 def test_scoreboard():
746
747 dut = TestLDSTCompUnit(16)
748 vl = rtlil.convert(dut, ports=dut.ports())
749 with open("test_ldst_comp.il", "w") as f:
750 f.write(vl)
751
752 run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
753
754
755 class TestLDSTCompUnitRegSpec(LDSTCompUnit):
756
757 def __init__(self):
758 from soc.experiment.l0_cache import TstL0CacheBuffer
759 from soc.fu.ldst.pipe_data import LDSTPipeSpec
760 regspec = LDSTPipeSpec.regspec
761 self.l0 = l0 = TstL0CacheBuffer()
762 pi = l0.l0.dports[0].pi
763 LDSTCompUnit.__init__(self, pi, regspec, 4)
764
765 def elaborate(self, platform):
766 m = LDSTCompUnit.elaborate(self, platform)
767 m.submodules.l0 = self.l0
768 m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
769 return m
770
771
772 def test_scoreboard_regspec():
773
774 dut = TestLDSTCompUnitRegSpec()
775 vl = rtlil.convert(dut, ports=dut.ports())
776 with open("test_ldst_comp.il", "w") as f:
777 f.write(vl)
778
779 run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
780
781
782 if __name__ == '__main__':
783 test_scoreboard_regspec()
784 test_scoreboard()