src/soc/experiment/l0_cache.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15
  16 """
  17
  18 from nmigen.compat.sim import run_simulation, Settle
  19 from nmigen.cli import verilog, rtlil
  20 from nmigen import Module, Signal, Mux, Elaboratable, Array, Cat
  21 from nmutil.iocontrol import RecordObject
  22 from nmigen.utils import log2_int
  23 from nmigen.hdl.rec import Record, Layout
  24
  25 from nmutil.latch import SRLatch, latchregister
  26 from soc.decoder.power_decoder2 import Data
  27 from soc.decoder.power_enums import InternalOp
  28 from soc.regfile.regfile import ortreereduce
  29 from nmutil.util import treereduce
  30
  31 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  32 from soc.decoder.power_decoder2 import Data
  33 #from nmutil.picker import PriorityPicker
  34 from nmigen.lib.coding import PriorityEncoder
  35 from soc.scoreboard.addr_split import LDSTSplitter
  36 from soc.scoreboard.addr_match import LenExpand
  37
  38 # for testing purposes
  39 from soc.experiment.testmem import TestMemory
  40
  41 import unittest
  42
  43
  44 class PortInterface(RecordObject):
  45     """PortInterface
  46
  47     defines the interface - the API - that the LDSTCompUnit connects
  48     to.  note that this is NOT a "fire-and-forget" interface.  the
  49     LDSTCompUnit *must* be kept appraised that the request is in
  50     progress, and only when it has a 100% successful completion rate
  51     can the notification be given (busy dropped).
  52
  53     The interface FSM rules are as follows:
  54
  55     * if busy_o is asserted, a LD/ST is in progress.  further
  56       requests may not be made until busy_o is deasserted.
  57
  58     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  59       will immediately be asserted and remain asserted.
  60
  61     * addr.ok is to be asserted when the LD/ST address is known.
  62       addr.data is to be valid on the same cycle.
  63
  64       addr.ok and addr.data must REMAIN asserted until busy_o
  65       is de-asserted.  this ensures that there is no need
  66       for the L0 Cache/Buffer to have an additional address latch
  67       (because the LDSTCompUnit already has it)
  68
  69     * addr_ok_o (or addr_exc_o) must be waited for.  these will
  70       be asserted *only* for one cycle and one cycle only.
  71
  72     * addr_exc_o will be asserted if there is no chance that the
  73       memory request may be fulfilled.
  74
  75       busy_o is deasserted on the same cycle as addr_exc_o is asserted.
  76
  77     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  78       HUNDRED PERCENT guarantee that the memory request will be
  79       fulfilled.
  80
  81     * for a LD, ld.ok will be asserted - for only one clock cycle -
  82       at any point in the future that is acceptable to the underlying
  83       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  84
  85       busy_o is deasserted on the same cycle as ld.ok is asserted.
  86
  87     * for a ST, st.ok may be asserted only after addr_ok_o had been
  88       asserted, alongside valid st.data at the same time.  st.ok
  89       must only be asserted for one cycle.
  90
  91       the underlying Memory is REQUIRED to pick up that data and
  92       guarantee its delivery.  no back-acknowledgement is required.
  93
  94       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  95     """
  96
  97     def __init__(self, name=None, regwid=64, addrwid=48):
  98
  99         self._regwid = regwid
 100         self._addrwid = addrwid
 101
 102         RecordObject.__init__(self, name=name)
 103
 104         # distinguish op type (ld/st)
 105         self.is_ld_i = Signal(reset_less=True)
 106         self.is_st_i = Signal(reset_less=True)
 107         self.op = CompLDSTOpSubset()  # hm insn_type ld/st duplicates here
 108
 109         # common signals
 110         self.busy_o = Signal(reset_less=True)     # do not use if busy
 111         self.go_die_i = Signal(reset_less=True)   # back to reset
 112         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 113         # addr is valid (TLB, L1 etc.)
 114         self.addr_ok_o = Signal(reset_less=True)
 115         self.addr_exc_o = Signal(reset_less=True)  # TODO, "type" of exception
 116
 117         # LD/ST
 118         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 119         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 120
 121 # TODO: elaborate function
 122
 123
 124 class DualPortSplitter(Elaboratable):
 125     """DualPortSplitter
 126
 127     * one incoming PortInterface
 128     * two *OUTGOING* PortInterfaces
 129     * uses LDSTSplitter to do it
 130
 131     (actually, thinking about it LDSTSplitter could simply be
 132      modified to conform to PortInterface: one in, two out)
 133
 134     once that is done each pair of ports may be wired directly
 135     to the dual ports of L0CacheBuffer
 136
 137     The split is carried out so that, regardless of alignment or
 138     mis-alignment, outgoing PortInterface[0] takes bit 4 == 0
 139     of the address, whilst outgoing PortInterface[1] takes
 140     bit 4 == 1.
 141
 142     PortInterface *may* need to be changed so that the length is
 143     a binary number (accepting values 1-16).
 144     """
 145     def __init__(self):
 146         self.outp = [PortInterface(name="outp_0"),
 147                      PortInterface(name="outp_1")]
 148         self.inp  = PortInterface(name="inp")
 149         print(self.outp)
 150
 151     def elaborate(self, platform):
 152         m = Module()
 153         comb = m.d.comb
 154         m.submodules.splitter = splitter = LDSTSplitter(64, 48, 4)
 155         comb += splitter.addr_i.eq(self.inp.addr) #XXX
 156         #comb += splitter.len_i.eq()
 157         #comb += splitter.valid_i.eq()
 158         comb += splitter.is_ld_i.eq(self.inp.is_ld_i)
 159         comb += splitter.is_st_i.eq(self.inp.is_st_i)
 160         #comb += splitter.st_data_i.eq()
 161         #comb += splitter.sld_valid_i.eq()
 162         #comb += splitter.sld_data_i.eq()
 163         #comb += splitter.sst_valid_i.eq()
 164         return m
 165
 166
 167 class DataMergerRecord(Record):
 168     """
 169     {data: 128 bit, byte_enable: 16 bit}
 170     """
 171
 172     def __init__(self, name=None):
 173         layout = (('data', 128),
 174                   ('en', 16))
 175         Record.__init__(self, Layout(layout), name=name)
 176
 177         self.data.reset_less = True
 178         self.en.reset_less = True
 179
 180
 181 # TODO: formal verification
 182 class DataMerger(Elaboratable):
 183     """DataMerger
 184
 185     Merges data based on an address-match matrix.
 186     Identifies (picks) one (any) row, then uses that row,
 187     based on matching address bits, to merge (OR) all data
 188     rows into the output.
 189
 190     Basically, by the time DataMerger is used, all of its incoming data is
 191     determined not to conflict.  The last step before actually submitting
 192     the request to the Memory Subsystem is to work out which requests,
 193     on the same 128-bit cache line, can be "merged" due to them being:
 194     (A) on the same address (bits 4 and above) (B) having byte-enable
 195     lines that (as previously mentioned) do not conflict.
 196
 197     Therefore, put simply, this module will:
 198     (1) pick a row (any row) and identify it by an index labelled "idx"
 199     (2) merge all byte-enable lines which are on that same address, as
 200         indicated by addr_match_i[idx], onto the output
 201     """
 202
 203     def __init__(self, array_size):
 204         """
 205         :addr_array_i: an NxN Array of Signals with bits set indicating address
 206                        match.  bits across the diagonal (addr_array_i[x][x])
 207                        will always be set, to indicate "active".
 208         :data_i: an Nx Array of Records {data: 128 bit, byte_enable: 16 bit}
 209         :data_o: an Output Record of same type
 210                  {data: 128 bit, byte_enable: 16 bit}
 211         """
 212         self.array_size = array_size
 213         ul = []
 214         for i in range(array_size):
 215             ul.append(Signal(array_size,
 216                              reset_less=True,
 217                              name="addr_match_%d" % i))
 218         self.addr_array_i = Array(ul)
 219
 220         ul = []
 221         for i in range(array_size):
 222             ul.append(DataMergerRecord())
 223         self.data_i = Array(ul)
 224         self.data_o = DataMergerRecord()
 225
 226     def elaborate(self, platform):
 227         m = Module()
 228         comb = m.d.comb
 229         #(1) pick a row
 230         m.submodules.pick = pick = PriorityEncoder(self.array_size)
 231         for j in range(self.array_size):
 232             comb += pick.i[j].eq(self.addr_array_i[j].bool())
 233         valid = ~pick.n
 234         idx = pick.o
 235         #(2) merge
 236         with m.If(valid):
 237             l = []
 238             for j in range(self.array_size):
 239                 select = self.addr_array_i[idx][j]
 240                 r = DataMergerRecord()
 241                 with m.If(select):
 242                     comb += r.eq(self.data_i[j])
 243                 l.append(r)
 244             comb += self.data_o.data.eq(ortreereduce(l,"data"))
 245             comb += self.data_o.en.eq(ortreereduce(l,"en"))
 246
 247         return m
 248
 249
 250 class LDSTPort(Elaboratable):
 251     def __init__(self, idx, regwid=64, addrwid=48):
 252         self.pi = PortInterface("ldst_port%d" % idx, regwid, addrwid)
 253
 254     def elaborate(self, platform):
 255         m = Module()
 256         comb, sync = m.d.comb, m.d.sync
 257
 258         # latches
 259         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 260         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 261         comb += cyc_l.s.eq(0)
 262         comb += cyc_l.r.eq(0)
 263
 264         # this is a little weird: we let the L0Cache/Buffer set
 265         # the outputs: this module just monitors "state".
 266
 267         # LD/ST requested activates "busy"
 268         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 269             comb += busy_l.s.eq(1)
 270
 271         # monitor for an exception or the completion of LD.
 272         with m.If(self.pi.addr_exc_o):
 273             comb += busy_l.r.eq(1)
 274
 275         # however ST needs one cycle before busy is reset
 276         with m.If(self.pi.st.ok | self.pi.ld.ok):
 277             comb += cyc_l.s.eq(1)
 278
 279         with m.If(cyc_l.q):
 280             comb += cyc_l.r.eq(1)
 281             comb += busy_l.r.eq(1)
 282
 283         # busy latch outputs to interface
 284         comb += self.pi.busy_o.eq(busy_l.q)
 285
 286         return m
 287
 288     def __iter__(self):
 289         yield self.pi.is_ld_i
 290         yield self.pi.is_st_i
 291         yield from self.pi.op.ports()
 292         yield self.pi.busy_o
 293         yield self.pi.go_die_i
 294         yield from self.pi.addr.ports()
 295         yield self.pi.addr_ok_o
 296         yield self.pi.addr_exc_o
 297
 298         yield from self.pi.ld.ports()
 299         yield from self.pi.st.ports()
 300
 301     def ports(self):
 302         return list(self)
 303
 304 # TODO: turn this into a module
 305 def byte_reverse(m, name, data, length):
 306     comb = m.d.comb
 307     data_r = Signal.like(data, name=name)
 308     with m.Switch(length):
 309         for j in [1,2,4,8]:
 310             with m.Case(j):
 311                 for i in range(j):
 312                     dest = data_r.word_select(i, 8)
 313                     src = data.word_select(j-1-i, 8)
 314                     comb += dest.eq(src)
 315     return data_r
 316
 317
 318 class L0CacheBuffer(Elaboratable):
 319     """L0 Cache / Buffer
 320
 321     Note that the final version will have *two* interfaces per LDSTCompUnit,
 322     to cover mis-aligned requests, as well as *two* 128-bit L1 Cache
 323     interfaces: one for odd (addr[4] == 1) and one for even (addr[4] == 1).
 324
 325     This version is to be used for test purposes (and actively maintained
 326     for such, rather than "replaced")
 327
 328     There are much better ways to implement this.  However it's only
 329     a "demo" / "test" class, and one important aspect: it responds
 330     combinatorially, where a nmigen FSM's state-changes only activate
 331     on clock-sync boundaries.
 332     """
 333
 334     def __init__(self, n_units, mem, regwid=64, addrwid=48):
 335         self.n_units = n_units
 336         self.mem = mem
 337         self.regwid = regwid
 338         self.addrwid = addrwid
 339         ul = []
 340         for i in range(n_units):
 341             ul.append(LDSTPort(i, regwid, addrwid))
 342         self.dports = Array(ul)
 343
 344     @property
 345     def addrbits(self):
 346         return log2_int(self.mem.regwid//8)
 347
 348     def splitaddr(self, addr):
 349         """split the address into top and bottom bits of the memory granularity
 350         """
 351         return addr[:self.addrbits], addr[self.addrbits:]
 352
 353     def elaborate(self, platform):
 354         m = Module()
 355         comb, sync = m.d.comb, m.d.sync
 356
 357         # connect the ports as modules
 358         for i in range(self.n_units):
 359             setattr(m.submodules, "port%d" % i, self.dports[i])
 360
 361         # state-machine latches
 362         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 363         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 364         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 365         m.submodules.idx_l = idx_l = SRLatch(False, name="idx_l")
 366         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 367
 368         # find one LD (or ST) and do it.  only one per cycle.
 369         # TODO: in the "live" (production) L0Cache/Buffer, merge multiple
 370         # LD/STs using mask-expansion - see LenExpand class
 371
 372         m.submodules.ldpick = ldpick = PriorityEncoder(self.n_units)
 373         m.submodules.stpick = stpick = PriorityEncoder(self.n_units)
 374         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 375
 376         lds = Signal(self.n_units, reset_less=True)
 377         sts = Signal(self.n_units, reset_less=True)
 378         ldi = []
 379         sti = []
 380         for i in range(self.n_units):
 381             pi = self.dports[i].pi
 382             ldi.append(pi.is_ld_i & pi.busy_o)  # accumulate ld-req signals
 383             sti.append(pi.is_st_i & pi.busy_o)  # accumulate st-req signals
 384         # put the requests into the priority-pickers
 385         comb += ldpick.i.eq(Cat(*ldi))
 386         comb += stpick.i.eq(Cat(*sti))
 387
 388         # hmm, have to select (record) the right port index
 389         nbits = log2_int(self.n_units, False)
 390         ld_idx = Signal(nbits, reset_less=False)
 391         st_idx = Signal(nbits, reset_less=False)
 392         # use these because of the sync-and-comb pass-through capability
 393         latchregister(m, ldpick.o, ld_idx, idx_l.qn, name="ld_idx_l")
 394         latchregister(m, stpick.o, st_idx, idx_l.qn, name="st_idx_l")
 395
 396         # convenience variables to reference the "picked" port
 397         ldport = self.dports[ld_idx].pi
 398         stport = self.dports[st_idx].pi
 399         # and the memory ports
 400         rdport = self.mem.rdport
 401         wrport = self.mem.wrport
 402
 403         # Priority-Pickers pick one and only one request, capture its index.
 404         # from that point on this code *only* "listens" to that port.
 405
 406         sync += adrok_l.s.eq(0)
 407         comb += adrok_l.r.eq(0)
 408         with m.If(~ldpick.n):
 409             comb += ld_active.s.eq(1)  # activate LD mode
 410             comb += idx_l.r.eq(1)  # pick (and capture) the port index
 411         with m.Elif(~stpick.n):
 412             comb += st_active.s.eq(1)  # activate ST mode
 413             comb += idx_l.r.eq(1)  # pick (and capture) the port index
 414
 415         # from this point onwards, with the port "picked", it stays picked
 416         # until ld_active (or st_active) are de-asserted.
 417
 418         # if now in "LD" mode: wait for addr_ok, then send the address out
 419         # to memory, acknowledge address, and send out LD data
 420         with m.If(ld_active.q):
 421             # set up LenExpander with the LD len and lower bits of addr
 422             lsbaddr, msbaddr = self.splitaddr(ldport.addr.data)
 423             comb += lenexp.len_i.eq(ldport.op.data_len)
 424             comb += lenexp.addr_i.eq(lsbaddr)
 425             with m.If(ldport.addr.ok & adrok_l.qn):
 426                 comb += rdport.addr.eq(msbaddr) # addr ok, send thru
 427                 comb += ldport.addr_ok_o.eq(1)  # acknowledge addr ok
 428                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 429
 430         # if now in "ST" mode: likewise do the same but with "ST"
 431         # to memory, acknowledge address, and send out LD data
 432         with m.If(st_active.q):
 433             # set up LenExpander with the ST len and lower bits of addr
 434             lsbaddr, msbaddr = self.splitaddr(stport.addr.data)
 435             comb += lenexp.len_i.eq(stport.op.data_len)
 436             comb += lenexp.addr_i.eq(lsbaddr)
 437             with m.If(stport.addr.ok):
 438                 comb += wrport.addr.eq(msbaddr)  # addr ok, send thru
 439                 with m.If(adrok_l.qn):
 440                     comb += stport.addr_ok_o.eq(1)  # acknowledge addr ok
 441                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 442
 443         # NOTE: in both these, below, the port itself takes care
 444         # of de-asserting its "busy_o" signal, based on either ld.ok going
 445         # high (by us, here) or by st.ok going high (by the LDSTCompUnit).
 446
 447         # for LD mode, when addr has been "ok'd", assume that (because this
 448         # is a "Memory" test-class) the memory read data is valid.
 449         comb += reset_l.s.eq(0)
 450         comb += reset_l.r.eq(0)
 451         with m.If(ld_active.q & adrok_l.q):
 452             # shift data down before pushing out.  requires masking
 453             # from the *byte*-expanded version of LenExpand output
 454             lddata = Signal(self.regwid, reset_less=True)
 455             comb += lddata.eq((rdport.data & lenexp.rexp_o) >>
 456                               (lenexp.addr_i*8))
 457             # yes this looks odd (inverted)
 458             with m.If(ldport.op.byte_reverse):
 459                 comb += ldport.ld.data.eq(lddata)  # put data out
 460             with m.Else():
 461                 # byte-reverse the data based on ld/st width
 462                 lddata_r = byte_reverse(m, 'lddata_r', lddata, lenexp.len_i)
 463                 comb += ldport.ld.data.eq(lddata_r)  # put reversed- data out
 464             comb += ldport.ld.ok.eq(1)           # indicate data valid
 465             comb += reset_l.s.eq(1)   # reset mode after 1 cycle
 466
 467         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 468         with m.If(st_active.q & stport.st.ok):
 469             # shift data up before storing.  lenexp *bit* version of mask is
 470             # passed straight through as byte-level "write-enable" lines.
 471             stport_d = stport.st.data
 472             stdata_i = Signal(self.regwid, reset_less=True)
 473             stdata = Signal(self.regwid, reset_less=True)
 474             # yes this looks odd (inverted)
 475             with m.If(ldport.op.byte_reverse):
 476                 comb += stdata_i.eq(stport_d)
 477             with m.Else():
 478                 # byte-reverse the data based on width
 479                 stdata_r = byte_reverse(m, 'stdata_r', stport_d, lenexp.len_i)
 480                 comb += stdata_i.eq(stdata_r)
 481             comb += stdata.eq(stdata_i << (lenexp.addr_i*8))
 482             comb += wrport.data.eq(stdata)  # write st to mem
 483             comb += wrport.en.eq(lenexp.lexp_o) # enable writes
 484             comb += reset_l.s.eq(1)   # reset mode after 1 cycle
 485
 486         # ugly hack, due to simultaneous addr req-go acknowledge
 487         reset_delay = Signal(reset_less=True)
 488         sync += reset_delay.eq(reset_l.q)
 489         with m.If(reset_delay):
 490             comb += adrok_l.r.eq(1)     # address reset
 491
 492         # after waiting one cycle (reset_l is "sync" mode), reset the port
 493         with m.If(reset_l.q):
 494             comb += idx_l.s.eq(1)  # deactivate port-index selector
 495             comb += ld_active.r.eq(1)   # leave the ST active for 1 cycle
 496             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 497             comb += reset_l.r.eq(1)     # clear reset
 498             comb += adrok_l.r.eq(1)     # address reset
 499
 500         return m
 501
 502     def ports(self):
 503         for p in self.dports:
 504             yield from p.ports()
 505
 506
 507 class TstL0CacheBuffer(Elaboratable):
 508     def __init__(self, n_units=3, regwid=16, addrwid=4):
 509         self.mem = TestMemory(regwid, addrwid, granularity=regwid//8)
 510         self.l0 = L0CacheBuffer(n_units, self.mem, regwid, addrwid<<1)
 511
 512     def elaborate(self, platform):
 513         m = Module()
 514         m.submodules.mem = self.mem
 515         m.submodules.l0 = self.l0
 516
 517         return m
 518
 519     def ports(self):
 520         yield from self.l0.ports()
 521         yield self.mem.rdport.addr
 522         yield self.mem.rdport.data
 523         yield self.mem.wrport.addr
 524         yield self.mem.wrport.data
 525         # TODO: mem ports
 526
 527
 528 def wait_busy(port, no=False):
 529     while True:
 530         busy = yield port.pi.busy_o
 531         print("busy", no, busy)
 532         if bool(busy) == no:
 533             break
 534         yield
 535
 536
 537 def wait_addr(port):
 538     while True:
 539         addr_ok = yield port.pi.addr_ok_o
 540         print("addrok", addr_ok)
 541         if not addr_ok:
 542             break
 543         yield
 544
 545
 546 def wait_ldok(port):
 547     while True:
 548         ldok = yield port.pi.ld.ok
 549         print("ldok", ldok)
 550         if ldok:
 551             break
 552         yield
 553
 554
 555 def l0_cache_st(dut, addr, data, datalen):
 556     l0 = dut.l0
 557     mem = dut.mem
 558     port0 = l0.dports[0]
 559     port1 = l0.dports[1]
 560
 561     # have to wait until not busy
 562     yield from wait_busy(port1, no=False)    # wait until not busy
 563
 564     # set up a ST on the port.  address first:
 565     yield port1.pi.is_st_i.eq(1)  # indicate ST
 566     yield port1.pi.op.data_len.eq(datalen)  # ST length (1/2/4/8)
 567
 568     yield port1.pi.addr.data.eq(addr)  # set address
 569     yield port1.pi.addr.ok.eq(1)  # set ok
 570     yield from wait_addr(port1)             # wait until addr ok
 571     # yield # not needed, just for checking
 572     # yield # not needed, just for checking
 573     # assert "ST" for one cycle (required by the API)
 574     yield port1.pi.st.data.eq(data)
 575     yield port1.pi.st.ok.eq(1)
 576     yield
 577     yield port1.pi.st.ok.eq(0)
 578
 579     # can go straight to reset.
 580     yield port1.pi.is_st_i.eq(0)  # end
 581     yield port1.pi.addr.ok.eq(0)  # set !ok
 582     # yield from wait_busy(port1, False)    # wait until not busy
 583
 584
 585 def l0_cache_ld(dut, addr, datalen, expected):
 586
 587     l0 = dut.l0
 588     mem = dut.mem
 589     port0 = l0.dports[0]
 590     port1 = l0.dports[1]
 591
 592     # have to wait until not busy
 593     yield from wait_busy(port1, no=False)    # wait until not busy
 594
 595     # set up a LD on the port.  address first:
 596     yield port1.pi.is_ld_i.eq(1)  # indicate LD
 597     yield port1.pi.op.data_len.eq(datalen)  # LD length (1/2/4/8)
 598
 599     yield port1.pi.addr.data.eq(addr)  # set address
 600     yield port1.pi.addr.ok.eq(1)  # set ok
 601     yield from wait_addr(port1)             # wait until addr ok
 602
 603     yield from wait_ldok(port1)             # wait until ld ok
 604     data = yield port1.pi.ld.data
 605
 606     # cleanup
 607     yield port1.pi.is_ld_i.eq(0)  # end
 608     yield port1.pi.addr.ok.eq(0)  # set !ok
 609     # yield from wait_busy(port1, no=False)    # wait until not busy
 610
 611     return data
 612
 613
 614 def l0_cache_ldst(arg, dut):
 615     yield
 616     addr = 0x2
 617     data = 0xbeef
 618     data2 = 0xf00f
 619     #data = 0x4
 620     yield from l0_cache_st(dut, 0x2, data, 2)
 621     yield from l0_cache_st(dut, 0x4, data2, 2)
 622     result = yield from l0_cache_ld(dut, 0x2, 2, data)
 623     result2 = yield from l0_cache_ld(dut, 0x4, 2, data2)
 624     yield
 625     arg.assertEqual(data, result, "data %x != %x" % (result, data))
 626     arg.assertEqual(data2, result2, "data2 %x != %x" % (result2, data2))
 627
 628
 629 def data_merger_merge(dut):
 630     print("data_merger")
 631     #starting with all inputs zero
 632     yield Settle()
 633     en = yield dut.data_o.en
 634     data = yield dut.data_o.data
 635     assert en == 0, "en must be zero"
 636     assert data == 0, "data must be zero"
 637     yield
 638
 639     yield dut.addr_array_i[0].eq(0xFF)
 640     for j in range(dut.array_size):
 641         yield dut.data_i[j].en.eq(1 << j)
 642         yield dut.data_i[j].data.eq(0xFF << (16*j))
 643     yield Settle()
 644
 645     en = yield dut.data_o.en
 646     data = yield dut.data_o.data
 647     assert data == 0xff00ff00ff00ff00ff00ff00ff00ff
 648     assert en == 0xff
 649     yield
 650
 651
 652 class TestL0Cache(unittest.TestCase):
 653
 654     def test_l0_cache(self):
 655
 656         dut = TstL0CacheBuffer(regwid=64)
 657         #vl = rtlil.convert(dut, ports=dut.ports())
 658         #with open("test_basic_l0_cache.il", "w") as f:
 659         #    f.write(vl)
 660
 661         run_simulation(dut, l0_cache_ldst(self, dut),
 662                        vcd_name='test_l0_cache_basic.vcd')
 663
 664
 665 class TestDataMerger(unittest.TestCase):
 666
 667     def test_data_merger(self):
 668
 669         dut = DataMerger(8)
 670         #vl = rtlil.convert(dut, ports=dut.ports())
 671         #with open("test_data_merger.il", "w") as f:
 672         #    f.write(vl)
 673
 674         run_simulation(dut, data_merger_merge(dut),
 675                        vcd_name='test_data_merger.vcd')
 676
 677
 678 class TestDualPortSplitter(unittest.TestCase):
 679
 680     def test_dual_port_splitter(self):
 681
 682         dut = DualPortSplitter()
 683         #vl = rtlil.convert(dut, ports=dut.ports())
 684         #with open("test_data_merger.il", "w") as f:
 685         #    f.write(vl)
 686
 687         #run_simulation(dut, data_merger_merge(dut),
 688         #               vcd_name='test_dual_port_splitter.vcd')
 689
 690
 691 if __name__ == '__main__':
 692     unittest.main(exit=False)
 693