src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15
  16 """
  17
  18 from nmigen.compat.sim import run_simulation, Settle
  19 from nmigen.cli import rtlil
  20 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
  21 from nmutil.iocontrol import RecordObject
  22 from nmigen.utils import log2_int
  23
  24 from nmutil.latch import SRLatch, latchregister
  25 from nmutil.util import rising_edge
  26 from soc.decoder.power_decoder2 import Data
  27 from soc.scoreboard.addr_match import LenExpand
  28 from soc.experiment.mem_types import LDSTException
  29
  30 # for testing purposes
  31 from soc.experiment.testmem import TestMemory
  32 #from soc.scoreboard.addr_split import LDSTSplitter
  33
  34 import unittest
  35
  36
  37 class PortInterface(RecordObject):
  38     """PortInterface
  39
  40     defines the interface - the API - that the LDSTCompUnit connects
  41     to.  note that this is NOT a "fire-and-forget" interface.  the
  42     LDSTCompUnit *must* be kept appraised that the request is in
  43     progress, and only when it has a 100% successful completion
  44     can the notification be given (busy dropped).
  45
  46     The interface FSM rules are as follows:
  47
  48     * if busy_o is asserted, a LD/ST is in progress.  further
  49       requests may not be made until busy_o is deasserted.
  50
  51     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  52       will immediately be asserted and remain asserted.
  53
  54     * addr.ok is to be asserted when the LD/ST address is known.
  55       addr.data is to be valid on the same cycle.
  56
  57       addr.ok and addr.data must REMAIN asserted until busy_o
  58       is de-asserted.  this ensures that there is no need
  59       for the L0 Cache/Buffer to have an additional address latch
  60       (because the LDSTCompUnit already has it)
  61
  62     * addr_ok_o (or exception.happened) must be waited for.  these will
  63       be asserted *only* for one cycle and one cycle only.
  64
  65     * exception.happened will be asserted if there is no chance that the
  66       memory request may be fulfilled.
  67
  68       busy_o is deasserted on the same cycle as exception.happened is asserted.
  69
  70     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  71       HUNDRED PERCENT guarantee that the memory request will be
  72       fulfilled.
  73
  74     * for a LD, ld.ok will be asserted - for only one clock cycle -
  75       at any point in the future that is acceptable to the underlying
  76       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  77
  78       busy_o is deasserted on the same cycle as ld.ok is asserted.
  79
  80     * for a ST, st.ok may be asserted only after addr_ok_o had been
  81       asserted, alongside valid st.data at the same time.  st.ok
  82       must only be asserted for one cycle.
  83
  84       the underlying Memory is REQUIRED to pick up that data and
  85       guarantee its delivery.  no back-acknowledgement is required.
  86
  87       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  88     """
  89
  90     def __init__(self, name=None, regwid=64, addrwid=48):
  91
  92         self._regwid = regwid
  93         self._addrwid = addrwid
  94
  95         RecordObject.__init__(self, name=name)
  96
  97         # distinguish op type (ld/st)
  98         self.is_ld_i = Signal(reset_less=True)
  99         self.is_st_i = Signal(reset_less=True)
 100
 101         # LD/ST data length (TODO: other things may be needed)
 102         self.data_len = Signal(4, reset_less=True)
 103
 104         # common signals
 105         self.busy_o = Signal(reset_less=True)     # do not use if busy
 106         self.go_die_i = Signal(reset_less=True)   # back to reset
 107         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 108         # addr is valid (TLB, L1 etc.)
 109         self.addr_ok_o = Signal(reset_less=True)
 110         self.exception_o = LDSTException("exc")
 111
 112         # LD/ST
 113         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 114         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 115
 116         # additional "modes"
 117         self.dcbz          = Signal()  # data cache block zero request
 118         self.nc            = Signal()  # no cacheing
 119         self.virt_mode     = Signal()  # virtual mode
 120         self.priv_mode     = Signal()  # privileged mode
 121
 122         # mmu
 123         self.mmu_done          = Signal() # keep for now
 124
 125         # dcache
 126         self.ldst_error        = Signal()
 127         ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
 128         self.cache_paradox     = Signal()
 129
 130     def connect_port(self, inport):
 131         print("connect_port", self, inport)
 132         return [self.is_ld_i.eq(inport.is_ld_i),
 133                 self.is_st_i.eq(inport.is_st_i),
 134                 self.data_len.eq(inport.data_len),
 135                 self.go_die_i.eq(inport.go_die_i),
 136                 self.addr.data.eq(inport.addr.data),
 137                 self.addr.ok.eq(inport.addr.ok),
 138                 self.st.eq(inport.st),
 139                 inport.ld.eq(self.ld),
 140                 inport.busy_o.eq(self.busy_o),
 141                 inport.addr_ok_o.eq(self.addr_ok_o),
 142                 inport.exception_o.eq(self.exception_o),
 143                 ]
 144
 145
 146 class PortInterfaceBase(Elaboratable):
 147     """PortInterfaceBase
 148
 149     Base class for PortInterface-compliant Memory read/writers
 150     """
 151
 152     def __init__(self, regwid=64, addrwid=4):
 153         self.regwid = regwid
 154         self.addrwid = addrwid
 155         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 156
 157     @property
 158     def addrbits(self):
 159         return log2_int(self.regwid//8)
 160
 161     def splitaddr(self, addr):
 162         """split the address into top and bottom bits of the memory granularity
 163         """
 164         return addr[:self.addrbits], addr[self.addrbits:]
 165
 166     def connect_port(self, inport):
 167         return self.pi.connect_port(inport)
 168
 169     def set_wr_addr(self, m, addr, mask): pass
 170     def set_rd_addr(self, m, addr, mask): pass
 171     def set_wr_data(self, m, data, wen): pass
 172     def get_rd_data(self, m): pass
 173
 174     def elaborate(self, platform):
 175         m = Module()
 176         comb, sync = m.d.comb, m.d.sync
 177
 178         # state-machine latches
 179         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 180         m.submodules.st_done = st_done = SRLatch(False, name="st_done")
 181         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 182         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 183         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 184         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 185         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 186
 187         self.busy_l = busy_l
 188
 189         sync += st_done.s.eq(0)
 190         comb += st_done.r.eq(0)
 191         comb += st_active.r.eq(0)
 192         comb += ld_active.r.eq(0)
 193         comb += cyc_l.s.eq(0)
 194         comb += cyc_l.r.eq(0)
 195         comb += busy_l.s.eq(0)
 196         comb += busy_l.r.eq(0)
 197         sync += adrok_l.s.eq(0)
 198         comb += adrok_l.r.eq(0)
 199
 200         # expand ld/st binary length/addr[:3] into unary bitmap
 201         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 202
 203         lds = Signal(reset_less=True)
 204         sts = Signal(reset_less=True)
 205         pi = self.pi
 206         comb += lds.eq(pi.is_ld_i)  # ld-req signals
 207         comb += sts.eq(pi.is_st_i)  # st-req signals
 208
 209         # detect busy "edge"
 210         busy_delay = Signal()
 211         busy_edge = Signal()
 212         sync += busy_delay.eq(pi.busy_o)
 213         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 214
 215         # activate mode: only on "edge"
 216         comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
 217         comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 218
 219         # LD/ST requested activates "busy" (only if not already busy)
 220         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 221             comb += busy_l.s.eq(~busy_delay)
 222
 223         # if now in "LD" mode: wait for addr_ok, then send the address out
 224         # to memory, acknowledge address, and send out LD data
 225         with m.If(ld_active.q):
 226             # set up LenExpander with the LD len and lower bits of addr
 227             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 228             comb += lenexp.len_i.eq(pi.data_len)
 229             comb += lenexp.addr_i.eq(lsbaddr)
 230             with m.If(pi.addr.ok & adrok_l.qn):
 231                 self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o)
 232                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 233                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 234
 235         # if now in "ST" mode: likewise do the same but with "ST"
 236         # to memory, acknowledge address, and send out LD data
 237         with m.If(st_active.q):
 238             # set up LenExpander with the ST len and lower bits of addr
 239             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 240             comb += lenexp.len_i.eq(pi.data_len)
 241             comb += lenexp.addr_i.eq(lsbaddr)
 242             with m.If(pi.addr.ok):
 243                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o)
 244                 with m.If(adrok_l.qn):
 245                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 246                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 247
 248         # for LD mode, when addr has been "ok'd", assume that (because this
 249         # is a "Memory" test-class) the memory read data is valid.
 250         comb += reset_l.s.eq(0)
 251         comb += reset_l.r.eq(0)
 252         lddata = Signal(self.regwid, reset_less=True)
 253         data, ldok = self.get_rd_data(m)
 254         comb += lddata.eq((data & lenexp.rexp_o) >>
 255                           (lenexp.addr_i*8))
 256         with m.If(ld_active.q & adrok_l.q):
 257             # shift data down before pushing out.  requires masking
 258             # from the *byte*-expanded version of LenExpand output
 259             comb += pi.ld.data.eq(lddata)  # put data out
 260             comb += pi.ld.ok.eq(ldok)      # indicate data valid
 261             comb += reset_l.s.eq(ldok)     # reset mode after 1 cycle
 262
 263         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 264         with m.If(st_active.q & pi.st.ok):
 265             # shift data up before storing.  lenexp *bit* version of mask is
 266             # passed straight through as byte-level "write-enable" lines.
 267             stdata = Signal(self.regwid, reset_less=True)
 268             comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
 269             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 270             # and also handle the ready/stall/busy protocol
 271             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
 272             sync += st_done.s.eq(1)     # store done trigger
 273         with m.If(st_done.q):
 274             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle
 275
 276         # ugly hack, due to simultaneous addr req-go acknowledge
 277         reset_delay = Signal(reset_less=True)
 278         sync += reset_delay.eq(reset_l.q)
 279         with m.If(reset_delay):
 280             comb += adrok_l.r.eq(1)     # address reset
 281
 282         # after waiting one cycle (reset_l is "sync" mode), reset the port
 283         with m.If(reset_l.q):
 284             comb += ld_active.r.eq(1)   # leave the ST active for 1 cycle
 285             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 286             comb += reset_l.r.eq(1)     # clear reset
 287             comb += adrok_l.r.eq(1)     # address reset
 288             comb += st_done.r.eq(1)     # store done reset
 289
 290         # monitor for an exception or the completion of LD.
 291         with m.If(self.pi.exception_o.happened):
 292             comb += busy_l.r.eq(1)
 293
 294         # however ST needs one cycle before busy is reset
 295         #with m.If(self.pi.st.ok | self.pi.ld.ok):
 296         with m.If(reset_l.s):
 297             comb += cyc_l.s.eq(1)
 298
 299         with m.If(cyc_l.q):
 300             comb += cyc_l.r.eq(1)
 301             comb += busy_l.r.eq(1)
 302
 303         # busy latch outputs to interface
 304         comb += pi.busy_o.eq(busy_l.q)
 305
 306         return m
 307
 308     def ports(self):
 309         yield from self.pi.ports()
 310
 311
 312 class TestMemoryPortInterface(PortInterfaceBase):
 313     """TestMemoryPortInterface
 314
 315     This is a test class for simple verification of the LDSTCompUnit
 316     and for the simple core, to be able to run unit tests rapidly and
 317     with less other code in the way.
 318
 319     Versions of this which are *compatible* (conform with PortInterface)
 320     will include augmented-Wishbone Bus versions, including ones that
 321     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 322     possible version that complies with PortInterface".
 323     """
 324
 325     def __init__(self, regwid=64, addrwid=4):
 326         super().__init__(regwid, addrwid)
 327         # hard-code memory addressing width to 6 bits
 328         self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
 329
 330     def set_wr_addr(self, m, addr, mask):
 331         lsbaddr, msbaddr = self.splitaddr(addr)
 332         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 333
 334     def set_rd_addr(self, m, addr, mask):
 335         lsbaddr, msbaddr = self.splitaddr(addr)
 336         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 337
 338     def set_wr_data(self, m, data, wen):
 339         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 340         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 341         return Const(1, 1)
 342
 343     def get_rd_data(self, m):
 344         return self.mem.rdport.data, Const(1, 1)
 345
 346     def elaborate(self, platform):
 347         m = super().elaborate(platform)
 348
 349         # add TestMemory as submodule
 350         m.submodules.mem = self.mem
 351
 352         return m
 353
 354     def ports(self):
 355         yield from super().ports()
 356         # TODO: memory ports