src/soc/experiment/test/test_compalu_multi.py

   1 """Computation Unit (aka "ALU Manager").
   2
   3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
   4 monitored.  At no time may the ALU proceed without this module notifying
   5 the Dependency Matrices.  At no time is a result production "abandoned".
   6 This module blocks (indicates busy) starting from when it first receives
   7 an opcode until it receives notification that
   8 its result(s) have been successfully stored in the regfile(s)
   9
  10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
  11 """
  12
  13 from nmigen.compat.sim import run_simulation, Settle
  14 from nmigen.cli import rtlil
  15 from nmigen import Module
  16
  17 from soc.decoder.power_enums import InternalOp
  18
  19 from soc.experiment.compalu_multi import MultiCompUnit
  20 from soc.experiment.alu_hier import ALU, DummyALU
  21 from soc.fu.alu.alu_input_record import CompALUOpSubset
  22
  23
  24 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
  25     yield dut.issue_i.eq(0)
  26     yield
  27     yield dut.src_i[0].eq(a)
  28     yield dut.src_i[1].eq(b)
  29     yield dut.oper_i.insn_type.eq(op)
  30     yield dut.oper_i.invert_a.eq(inv_a)
  31     yield dut.oper_i.imm_data.imm.eq(imm)
  32     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
  33     yield dut.oper_i.zero_a.eq(zero_a)
  34     yield dut.issue_i.eq(1)
  35     yield
  36     yield dut.issue_i.eq(0)
  37     yield
  38     if not imm_ok or not zero_a:
  39         yield dut.rd.go.eq(0b11)
  40         while True:
  41             yield
  42             rd_rel_o = yield dut.rd.rel
  43             print ("rd_rel", rd_rel_o)
  44             if rd_rel_o:
  45                 break
  46         yield dut.rd.go.eq(0)
  47     if len(dut.src_i) == 3:
  48         yield dut.rd.go.eq(0b100)
  49         while True:
  50             yield
  51             rd_rel_o = yield dut.rd.rel
  52             print ("rd_rel", rd_rel_o)
  53             if rd_rel_o:
  54                 break
  55         yield dut.rd.go.eq(0)
  56
  57     req_rel_o = yield dut.wr.rel
  58     result = yield dut.data_o
  59     print ("req_rel", req_rel_o, result)
  60     while True:
  61         req_rel_o = yield dut.wr.rel
  62         result = yield dut.data_o
  63         print ("req_rel", req_rel_o, result)
  64         if req_rel_o:
  65             break
  66         yield
  67     yield dut.wr.go[0].eq(1)
  68     yield Settle()
  69     result = yield dut.data_o
  70     yield
  71     print ("result", result)
  72     yield dut.wr.go[0].eq(0)
  73     yield
  74     return result
  75
  76
  77 def scoreboard_sim_dummy(dut):
  78     result = yield from op_sim(dut, 5, 2, InternalOp.OP_NOP, inv_a=0,
  79                                     imm=8, imm_ok=1)
  80     assert result == 5, result
  81
  82     result = yield from op_sim(dut, 9, 2, InternalOp.OP_NOP, inv_a=0,
  83                                     imm=8, imm_ok=1)
  84     assert result == 9, result
  85
  86
  87 def scoreboard_sim(dut):
  88     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
  89                                     imm=8, imm_ok=1)
  90     assert result == 13
  91
  92     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
  93     assert result == 7
  94
  95     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
  96     assert result == 65532
  97
  98     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1,
  99                                     imm=8, imm_ok=1)
 100     assert result == 8
 101
 102     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, zero_a=1)
 103     assert result == 2
 104
 105
 106 def test_compunit():
 107
 108     m = Module()
 109     alu = ALU(16)
 110     dut = MultiCompUnit(16, alu, CompALUOpSubset)
 111     m.submodules.cu = dut
 112
 113     vl = rtlil.convert(dut, ports=dut.ports())
 114     with open("test_compunit1.il", "w") as f:
 115         f.write(vl)
 116
 117     run_simulation(m, scoreboard_sim(dut), vcd_name='test_compunit1.vcd')
 118
 119
 120 class CompUnitParallelTest:
 121     def __init__(self, dut):
 122         self.dut = dut
 123
 124         # Operation cycle should not take longer than this:
 125         self.MAX_BUSY_WAIT = 50
 126
 127         # Minimum duration in which issue_i will be kept inactive,
 128         # during which busy_o must remain low.
 129         self.MIN_BUSY_LOW = 5
 130
 131         # Number of cycles to stall until the assertion of go.
 132         # One value, for each port. Can be zero, for no delay.
 133         self.RD_GO_DELAY = [0, 3]
 134
 135         # store common data for the input operation of the processes
 136         # input operation:
 137         self.op = 0
 138         self.inv_a = self.zero_a = 0
 139         self.imm = self.imm_ok = 0
 140         # input data:
 141         self.a = self.b = 0
 142
 143     def driver(self):
 144         print("Begin parallel test.")
 145         yield from self.operation(5, 2, InternalOp.OP_ADD, inv_a=0,
 146                                   imm=8, imm_ok=1)
 147
 148     def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
 149         # store data for the operation
 150         self.a = a
 151         self.b = b
 152         self.op = op
 153         self.inv_a = inv_a
 154         self.imm = imm
 155         self.imm_ok = imm_ok
 156         self.zero_a = zero_a
 157
 158         # trigger operation cycle
 159         yield from self.issue()
 160
 161     def issue(self):
 162         # issue_i starts inactive
 163         yield self.dut.issue_i.eq(0)
 164
 165         for n in range(self.MIN_BUSY_LOW):
 166             yield
 167             # busy_o must remain inactive. It cannot rise on its own.
 168             busy_o = yield self.dut.busy_o
 169             assert not busy_o
 170
 171         # activate issue_i to begin the operation cycle
 172         yield self.dut.issue_i.eq(1)
 173
 174         # at the same time, present the operation
 175         yield self.dut.oper_i.insn_type.eq(self.op)
 176         yield self.dut.oper_i.invert_a.eq(self.inv_a)
 177         yield self.dut.oper_i.imm_data.imm.eq(self.imm)
 178         yield self.dut.oper_i.imm_data.imm_ok.eq(self.imm_ok)
 179         yield self.dut.oper_i.zero_a.eq(self.zero_a)
 180
 181         # give one cycle for the CompUnit to latch the data
 182         yield
 183
 184         # busy_o must keep being low in this cycle, because issue_i was
 185         # low on the previous cycle.
 186         # It cannot rise on its own.
 187         # Also, busy_o and issue_i must never be active at the same time, ever.
 188         busy_o = yield self.dut.busy_o
 189         assert not busy_o
 190
 191         # Lower issue_i
 192         yield self.dut.issue_i.eq(0)
 193
 194         # deactivate inputs along with issue_i, so we can be sure the data
 195         # was latched at the correct cycle
 196         yield self.dut.oper_i.insn_type.eq(0)
 197         yield self.dut.oper_i.invert_a.eq(0)
 198         yield self.dut.oper_i.imm_data.imm.eq(0)
 199         yield self.dut.oper_i.imm_data.imm_ok.eq(0)
 200         yield self.dut.oper_i.zero_a.eq(0)
 201         yield
 202
 203         # wait for busy_o to lower
 204         # timeout after self.MAX_BUSY_WAIT cycles
 205         for n in range(self.MAX_BUSY_WAIT):
 206             # sample busy_o in the current cycle
 207             busy_o = yield self.dut.busy_o
 208             if not busy_o:
 209                 # operation cycle ends when busy_o becomes inactive
 210                 break
 211             yield
 212
 213         # if busy_o is still active, a timeout has occurred
 214         # TODO: Uncomment this, once the test is complete:
 215         # assert not busy_o
 216
 217         if busy_o:
 218             print("If you are reading this, "
 219                   "it's because the above test failed, as expected,\n"
 220                   "with a timeout. It must pass, once the test is complete.")
 221             return
 222
 223         print("If you are reading this, "
 224               "it's because the above test unexpectedly passed.")
 225
 226     def rd(self, rd_idx):
 227         # wait for issue_i to rise
 228         while True:
 229             issue_i = yield self.dut.issue_i
 230             if issue_i:
 231                 break
 232             # issue_i has not risen yet, so rd must keep low
 233             rel = yield self.dut.rd.rel[rd_idx]
 234             assert not rel
 235             yield
 236
 237         # we do not want rd to rise on an immediate operand
 238         # if it is immediate, exit the process
 239         # TODO: don't exit the process, monitor rd instead to ensure it
 240         #       doesn't rise on its own
 241         if (self.zero_a and rd_idx == 0) or (self.imm_ok and rd_idx == 1):
 242             return
 243
 244         # issue_i has risen. rel must rise on the next cycle
 245         rel = yield self.dut.rd.rel[rd_idx]
 246         assert not rel
 247
 248         # stall for additional cycles. Check that rel doesn't fall on its own
 249         for n in range(self.RD_GO_DELAY[rd_idx]):
 250             yield
 251             rel = yield self.dut.rd.rel[rd_idx]
 252             assert rel
 253
 254         # Before asserting "go", make sure "rel" has risen.
 255         # The use of Settle allows "go" to be set combinatorially,
 256         # rising on the same cycle as "rel".
 257         yield Settle()
 258         rel = yield self.dut.rd.rel[rd_idx]
 259         assert rel
 260
 261         # assert go for one cycle
 262         yield self.dut.rd.go[rd_idx].eq(1)
 263         yield
 264
 265         # rel must keep high, since go was inactive in the last cycle
 266         rel = yield self.dut.rd.rel[rd_idx]
 267         assert rel
 268
 269         # finish the go one-clock pulse
 270         yield self.dut.rd.go[rd_idx].eq(0)
 271         yield
 272
 273         # rel must have gone low in response to go being high
 274         # on the previous cycle
 275         rel = yield self.dut.rd.rel[rd_idx]
 276         assert not rel
 277
 278         # TODO: also when dut.rd.go is set, put the expected value into
 279         # the src_i.  use dut.get_in[rd_idx] to do so
 280
 281     def wr(self, wr_idx):
 282         # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
 283         yield
 284         # TODO: also when dut.wr.go is set, check the output against the
 285         # self.expected_o and assert.  use dut.get_out(wr_idx) to do so.
 286
 287     def run_simulation(self, vcd_name):
 288         run_simulation(self.dut, [self.driver(),
 289                                   self.rd(0),  # one read port (a)
 290                                   self.rd(1),  # one read port (b)
 291                                   self.wr(0),  # one write port (o)
 292                                   ],
 293                        vcd_name=vcd_name)
 294
 295
 296 def test_compunit_regspec3():
 297
 298     inspec = [('INT', 'a', '0:15'),
 299               ('INT', 'b', '0:15'),
 300               ('INT', 'c', '0:15')]
 301     outspec = [('INT', 'o', '0:15'),
 302               ]
 303
 304     regspec = (inspec, outspec)
 305
 306     m = Module()
 307     alu = DummyALU(16)
 308     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 309     m.submodules.cu = dut
 310
 311     run_simulation(m, scoreboard_sim_dummy(dut),
 312                    vcd_name='test_compunit_regspec3.vcd')
 313
 314
 315 def test_compunit_regspec1():
 316
 317     inspec = [('INT', 'a', '0:15'),
 318               ('INT', 'b', '0:15')]
 319     outspec = [('INT', 'o', '0:15'),
 320               ]
 321
 322     regspec = (inspec, outspec)
 323
 324     m = Module()
 325     alu = ALU(16)
 326     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 327     m.submodules.cu = dut
 328
 329     vl = rtlil.convert(dut, ports=dut.ports())
 330     with open("test_compunit_regspec1.il", "w") as f:
 331         f.write(vl)
 332
 333     run_simulation(m, scoreboard_sim(dut),
 334                    vcd_name='test_compunit_regspec1.vcd')
 335
 336     test = CompUnitParallelTest(dut)
 337     test.run_simulation("test_compunit_parallel.vcd")
 338
 339
 340 if __name__ == '__main__':
 341     test_compunit()
 342     test_compunit_regspec1()
 343     test_compunit_regspec3()