Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / base_input_record.py
1 from nmigen.hdl.rec import Record, Layout
2 from nmigen import Signal
3
4
5 class CompOpSubsetBase(Record):
6 """CompOpSubsetBase
7
8 base class of subset Operation information
9 """
10 def __init__(self, layout, name):
11 if name is None:
12 name = self.__class__.__name__
13 print ("Subset name", name)
14 assert name.startswith("Comp")
15 assert name.endswith("OpSubset")
16 name = name[4:-8].lower() + "_op"
17
18 Record.__init__(self, Layout(layout), name=name)
19
20 # grrr. Record does not have kwargs
21 for fname, sig in self.fields.items():
22 sig.reset_less = True
23
24 def eq_from(self, other):
25 """ use this to copy in from another CompRecord
26 """
27 res = []
28 print ("eq_from self", self, self.fields)
29 print (" other", other, other.fields)
30 for fname, sig in self.fields.items():
31 eqfrom = other.fields[fname]
32 res.append(sig.eq(eqfrom))
33 return res
34
35 def eq_from_execute1(self, other):
36 """ use this to copy in from Decode2Execute1Type
37 """
38 return self.eq_from(other)
39
40 def ports(self):
41 res = []
42 for fname, sig in self.fields.items():
43 if isinstance(sig, Signal):
44 res.append(sig)
45 return res