2 from soc
.decoder
.power_enums
import (XER_bits
, Function
)
4 # XXX bad practice: use of global variables
5 from soc
.fu
.shift_rot
.test
.test_pipe_caller
import ShiftRotTestCase
6 from soc
.fu
.shift_rot
.test
.test_pipe_caller
import test_data
8 from soc
.fu
.compunits
.compunits
import ShiftRotFunctionUnit
9 from soc
.fu
.compunits
.test
.test_compunit
import TestRunner
12 class ShiftRotTestRunner(TestRunner
):
13 def __init__(self
, test_data
):
14 super().__init
__(test_data
, ShiftRotFunctionUnit
, self
,
17 def get_cu_inputs(self
, dec2
, sim
):
18 """naming (res) must conform to ShiftRotFunctionUnit input regspec
23 reg1_ok
= yield dec2
.e
.read_reg1
.ok
25 data1
= yield dec2
.e
.read_reg1
.data
26 res
['a'] = sim
.gpr(data1
).value
29 reg2_ok
= yield dec2
.e
.read_reg2
.ok
31 data2
= yield dec2
.e
.read_reg2
.data
32 res
['rs'] = sim
.gpr(data2
).value
35 reg3_ok
= yield dec2
.e
.read_reg3
.ok
37 data3
= yield dec2
.e
.read_reg3
.data
38 res
['rb'] = sim
.gpr(data3
).value
41 carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
42 carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
43 res
['xer_ca'] = carry |
(carry32
<<1)
47 def check_cu_outputs(self
, res
, dec2
, sim
, code
):
48 """naming (res) must conform to ShiftRotFunctionUnit output regspec
52 out_reg_valid
= yield dec2
.e
.write_reg
.ok
54 write_reg_idx
= yield dec2
.e
.write_reg
.data
55 expected
= sim
.gpr(write_reg_idx
).value
57 print(f
"expected {expected:x}, actual: {cu_out:x}")
58 self
.assertEqual(expected
, cu_out
, code
)
60 rc
= yield dec2
.e
.rc
.data
61 op
= yield dec2
.e
.insn_type
62 cridx_ok
= yield dec2
.e
.write_cr
.ok
63 cridx
= yield dec2
.e
.write_cr
.data
65 print ("check extra output", repr(code
), cridx_ok
, cridx
)
68 self
.assertEqual(cridx_ok
, 1, code
)
69 self
.assertEqual(cridx
, 0, code
)
73 cr_expected
= sim
.crl
[cridx
].get_range().value
74 cr_actual
= res
['cr0']
75 print ("CR", cridx
, cr_expected
, cr_actual
)
76 self
.assertEqual(cr_expected
, cr_actual
, "CR%d %s" % (cridx
, code
))
79 cry_out
= yield dec2
.e
.output_carry
81 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
82 xer_ca
= res
['xer_ca']
83 real_carry
= xer_ca
& 0b1 # XXX CO not CO32
84 self
.assertEqual(expected_carry
, real_carry
, code
)
85 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
86 real_carry32
= bool(xer_ca
& 0b10) # XXX CO32
87 self
.assertEqual(expected_carry32
, real_carry32
, code
)
89 # TODO: XER.ov and XER.so
90 oe
= yield dec2
.e
.oe
.data
92 xer_ov
= res
['xer_ov']
93 xer_so
= res
['xer_so']
96 if __name__
== "__main__":
97 unittest
.main(exit
=False)
98 suite
= unittest
.TestSuite()
99 suite
.addTest(ShiftRotTestRunner(test_data
))
101 runner
= unittest
.TextTestRunner()