1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.test
.utils
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.logical
.pipeline
import LogicalBasePipe
16 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
17 from soc
.fu
.alu
.pipe_data
import ALUPipeSpec
22 def __init__(self
, program
, regs
, sprs
, name
):
23 self
.program
= program
29 def get_rec_width(rec
):
31 # Setup random inputs for dut.op
38 def set_alu_inputs(alu
, dec2
, sim
):
39 # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
40 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
41 # and place it into data_i.b
43 reg3_ok
= yield dec2
.e
.read_reg3
.ok
44 reg1_ok
= yield dec2
.e
.read_reg1
.ok
45 assert reg3_ok
!= reg1_ok
47 data1
= yield dec2
.e
.read_reg3
.data
48 data1
= sim
.gpr(data1
).value
50 data1
= yield dec2
.e
.read_reg1
.data
51 data1
= sim
.gpr(data1
).value
55 yield alu
.p
.data_i
.a
.eq(data1
)
57 # If there's an immediate, set the B operand to that
58 reg2_ok
= yield dec2
.e
.read_reg2
.ok
59 imm_ok
= yield dec2
.e
.imm_data
.imm_ok
61 data2
= yield dec2
.e
.imm_data
.imm
63 data2
= yield dec2
.e
.read_reg2
.data
64 data2
= sim
.gpr(data2
).value
67 yield alu
.p
.data_i
.b
.eq(data2
)
70 def set_extra_alu_inputs(alu
, dec2
, sim
):
71 carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
72 carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
73 yield alu
.p
.data_i
.xer_ca
[0].eq(carry
)
74 yield alu
.p
.data_i
.xer_ca
[1].eq(carry32
)
75 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
76 yield alu
.p
.data_i
.xer_so
.eq(so
)
79 # This test bench is a bit different than is usual. Initially when I
80 # was writing it, I had all of the tests call a function to create a
81 # device under test and simulator, initialize the dut, run the
82 # simulation for ~2 cycles, and assert that the dut output what it
83 # should have. However, this was really slow, since it needed to
84 # create and tear down the dut and simulator for every test case.
86 # Now, instead of doing that, every test case in ALUTestCase puts some
87 # data into the test_data list below, describing the instructions to
88 # be tested and the initial state. Once all the tests have been run,
89 # test_data gets passed to TestRunner which then sets up the DUT and
90 # simulator once, runs all the data through it, and asserts that the
91 # results match the pseudocode sim at every cycle.
93 # By doing this, I've reduced the time it takes to run the test suite
94 # massively. Before, it took around 1 minute on my computer, now it
95 # takes around 3 seconds
100 class LogicalTestCase(FHDLTestCase
):
101 def __init__(self
, name
):
102 super().__init
__(name
)
103 self
.test_name
= name
105 def run_tst_program(self
, prog
, initial_regs
=[0] * 32, initial_sprs
={}):
106 tc
= TestCase(prog
, initial_regs
, initial_sprs
, self
.test_name
)
110 insns
= ["and", "or", "xor"]
112 choice
= random
.choice(insns
)
113 lst
= [f
"{choice} 3, 1, 2"]
114 initial_regs
= [0] * 32
115 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
116 initial_regs
[2] = random
.randint(0, (1 << 64)-1)
117 self
.run_tst_program(Program(lst
), initial_regs
)
119 def test_rand_imm_logical(self
):
120 insns
= ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
122 choice
= random
.choice(insns
)
123 imm
= random
.randint(0, (1 << 16)-1)
124 lst
= [f
"{choice} 3, 1, {imm}"]
126 initial_regs
= [0] * 32
127 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
128 self
.run_tst_program(Program(lst
), initial_regs
)
131 insns
= ["cntlzd", "cnttzd", "cntlzw", "cnttzw"]
133 choice
= random
.choice(insns
)
134 lst
= [f
"{choice} 3, 1"]
136 initial_regs
= [0] * 32
137 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
138 self
.run_tst_program(Program(lst
), initial_regs
)
140 def test_parity(self
):
141 insns
= ["prtyw", "prtyd"]
143 choice
= random
.choice(insns
)
144 lst
= [f
"{choice} 3, 1"]
146 initial_regs
= [0] * 32
147 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
148 self
.run_tst_program(Program(lst
), initial_regs
)
150 def test_popcnt(self
):
151 insns
= ["popcntb", "popcntw", "popcntd"]
153 choice
= random
.choice(insns
)
154 lst
= [f
"{choice} 3, 1"]
156 initial_regs
= [0] * 32
157 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
158 self
.run_tst_program(Program(lst
), initial_regs
)
160 def test_popcnt_edge(self
):
161 insns
= ["popcntb", "popcntw", "popcntd"]
163 lst
= [f
"{choice} 3, 1"]
164 initial_regs
= [0] * 32
166 self
.run_tst_program(Program(lst
), initial_regs
)
169 lst
= ["cmpb 3, 1, 2"]
170 initial_regs
= [0] * 32
171 initial_regs
[1] = 0xdeadbeefcafec0de
172 initial_regs
[2] = 0xd0adb0000afec1de
173 self
.run_tst_program(Program(lst
), initial_regs
)
175 def test_bpermd(self
):
176 lst
= ["bpermd 3, 1, 2"]
177 initial_regs
= [0] * 32
178 initial_regs
[1] = 0xdeadbeefcafec0de
179 initial_regs
[2] = 0xd0adb0000afec1de
180 self
.run_tst_program(Program(lst
), initial_regs
)
182 def test_ilang(self
):
183 rec
= CompALUOpSubset()
185 pspec
= ALUPipeSpec(id_wid
=2, op_wid
=get_rec_width(rec
))
186 alu
= LogicalBasePipe(pspec
)
187 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
188 with
open("logical_pipeline.il", "w") as f
:
192 class TestRunner(FHDLTestCase
):
193 def __init__(self
, test_data
):
194 super().__init
__("run_all")
195 self
.test_data
= test_data
200 instruction
= Signal(32)
202 pdecode
= create_pdecode()
204 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
206 rec
= CompALUOpSubset()
208 pspec
= ALUPipeSpec(id_wid
=2, op_wid
=get_rec_width(rec
))
209 m
.submodules
.alu
= alu
= LogicalBasePipe(pspec
)
211 comb
+= alu
.p
.data_i
.ctx
.op
.eq_from_execute1(pdecode2
.e
)
212 comb
+= alu
.p
.valid_i
.eq(1)
213 comb
+= alu
.n
.ready_i
.eq(1)
214 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
220 for test
in self
.test_data
:
222 program
= test
.program
223 self
.subTest(test
.name
)
224 simulator
= ISA(pdecode2
, test
.regs
, test
.sprs
, 0)
225 gen
= program
.generate_instructions()
226 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
228 index
= simulator
.pc
.CIA
.value
//4
229 while index
< len(instructions
):
230 ins
, code
= instructions
[index
]
232 print("0x{:X}".format(ins
& 0xffffffff))
235 # ask the decoder to decode this binary data (endian'd)
236 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
237 yield instruction
.eq(ins
) # raw binary instr.
239 fn_unit
= yield pdecode2
.e
.fn_unit
240 self
.assertEqual(fn_unit
, Function
.LOGICAL
.value
, code
)
241 yield from set_alu_inputs(alu
, pdecode2
, simulator
)
242 yield from set_extra_alu_inputs(alu
, pdecode2
, simulator
)
244 opname
= code
.split(' ')[0]
245 yield from simulator
.call(opname
)
246 index
= simulator
.pc
.CIA
.value
//4
248 vld
= yield alu
.n
.valid_o
251 vld
= yield alu
.n
.valid_o
253 alu_out
= yield alu
.n
.data_o
.o
254 out_reg_valid
= yield pdecode2
.e
.write_reg
.ok
256 write_reg_idx
= yield pdecode2
.e
.write_reg
.data
257 expected
= simulator
.gpr(write_reg_idx
).value
258 print(f
"expected {expected:x}, actual: {alu_out:x}")
259 self
.assertEqual(expected
, alu_out
, code
)
260 yield from self
.check_extra_alu_outputs(alu
, pdecode2
,
263 sim
.add_sync_process(process
)
264 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
268 def check_extra_alu_outputs(self
, alu
, dec2
, sim
, code
):
269 rc
= yield dec2
.e
.rc
.data
271 cr_expected
= sim
.crl
[0].get_range().value
272 cr_actual
= yield alu
.n
.data_o
.cr0
.data
273 self
.assertEqual(cr_expected
, cr_actual
, code
)
276 if __name__
== "__main__":
277 unittest
.main(exit
=False)
278 suite
= unittest
.TestSuite()
279 suite
.addTest(TestRunner(test_data
))
281 runner
= unittest
.TextTestRunner()