src/soc/fu/mmu/pipe_data.py

   1 """MMU Pipeline Data structures
   2
   3 Covers MFMMU and MTMMU for MMU MMUs (dsisr, dar), and DCBZ and TLBIE.
   4
   5 Note: RB is *redirected* (in the decoder CSV files) to the field that
   6 happens, here, to be named "ra"!  yes wonderfully confusing.  similar
   7 thing goes on with shift_rot.
   8
   9 Links:
  10 * https://bugs.libre-soc.org/show_bug.cgi?id=491
  11 * https://libre-soc.org/3d_gpu/architecture/regfile/
  12 """
  13
  14 from soc.fu.pipe_data import IntegerData
  15 from soc.fu.mmu.mmu_input_record import CompMMUOpSubset
  16 from soc.fu.alu.pipe_data import CommonPipeSpec
  17
  18
  19 class MMUInputData(IntegerData):
  20     regspec = [('INT', 'ra', '0:63'),        # RA
  21                ('SPR', 'spr1', '0:63'),      # MMU (slow)
  22                ('FAST', 'fast1', '0:63'),    # MMU (fast: LR, CTR etc)
  23                ]
  24     def __init__(self, pspec):
  25         super().__init__(pspec, False)
  26         # convenience
  27         self.a = self.ra
  28
  29
  30 class MMUOutputData(IntegerData):
  31     regspec = [('INT', 'o', '0:63'),        # RT
  32                ('SPR', 'spr1', '0:63'),     # MMU (slow)
  33                ('FAST', 'fast1', '0:63'),   # MMU (fast: LR, CTR etc)
  34                ]
  35     def __init__(self, pspec):
  36         super().__init__(pspec, True)
  37
  38
  39 class MMUPipeSpec(CommonPipeSpec):
  40     regspec = (MMUInputData.regspec, MMUOutputData.regspec)
  41     opsubsetkls = CompMMUOpSubset