Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / mul / pipeline.py
1 from nmutil.singlepipe import ControlBase
2 from nmutil.pipemodbase import PipeModBaseChain
3 from soc.fu.div.input_stage import DivMulInputStage
4 from soc.fu.mul.output_stage import DivMulOutputStage
5 from soc.fu.mul.pre_stage import MulMainStage1
6 from soc.fu.mul.main_stage import MulMainStage2
7 from soc.fu.mul.post_stage import MulMainStage3
8
9
10 class MulStages1(PipeModBaseChain):
11 def get_chain(self):
12 inp = DivMulInputStage(self.pspec) # a-invert (no carry)
13 main = MulMainStage1(self.pspec) # detect signed/32-bit
14 return [inp, main]
15
16
17 class MulStages2(PipeModBaseChain):
18 def get_chain(self):
19 main2 = MulMainStage2(self.pspec) # actual multiply
20 return [main2]
21
22
23 class MulStages3(PipeModBaseChain):
24 def get_chain(self):
25 main3 = MulMainStage3(self.pspec) # select output bits, invert, set ov
26 out = DivMulOutputStage(self.pspec) # do CR, XER and out-invert etc.
27 return [main3, out]
28
29
30 class MulBasePipe(ControlBase):
31 def __init__(self, pspec):
32 ControlBase.__init__(self)
33 self.pspec = pspec
34 self.pipe1 = MulStages1(pspec)
35 self.pipe2 = MulStages2(pspec)
36 self.pipe3 = MulStages3(pspec)
37 self._eqs = self.connect([self.pipe1, self.pipe2, self.pipe3])
38
39 def elaborate(self, platform):
40 m = ControlBase.elaborate(self, platform)
41 m.submodules.mul_pipe1 = self.pipe1
42 m.submodules.mul_pipe2 = self.pipe2
43 m.submodules.mul_pipe3 = self.pipe3
44 m.d.comb += self._eqs
45 return m