Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / mul / test / test_pipe_ilang.py
1 import unittest
2 from nmigen.cli import rtlil
3 from soc.fu.mul.pipe_data import MulPipeSpec
4 from soc.fu.mul.pipeline import MulBasePipe
5
6
7 class TestPipeIlang(unittest.TestCase):
8 def write_ilang(self):
9 pspec = MulPipeSpec(id_wid=2, parent_pspec=None)
10 alu = MulBasePipe(pspec)
11 vl = rtlil.convert(alu, ports=alu.ports())
12 with open("mul_pipeline.il", "w") as f:
13 f.write(vl)
14
15 def test_ilang(self):
16 self.write_ilang()
17
18
19 if __name__ == "__main__":
20 unittest.main()