src/soc/fu/shift_rot/output_stage.py

   1 # This stage is intended to handle the gating of carry and overflow
   2 # out, summary overflow generation, and updating the condition
   3 # register
   4 from soc.fu.common_output_stage import CommonOutputStage
   5 from soc.fu.shift_rot.pipe_data import (ShiftRotOutputData,
   6                                       ShiftRotOutputDataFinal)
   7
   8
   9 class ShiftRotOutputStage(CommonOutputStage):
  10
  11     def ispec(self):
  12         return ShiftRotOutputData(self.pspec)
  13
  14     def ospec(self):
  15         return ShiftRotOutputDataFinal(self.pspec)
  16