src/soc/fu/spr/pipe_data.py

   1 """SPR Pipeline Data structures
   2
   3 Covers MFSPR and MTSPR.  however given that the SPRs are split across
   4 XER (which is 3 separate registers), Fast-SPR and Slow-SPR regfiles,
   5 the data structures are slightly more involved than just "INT, SPR".
   6
   7 Links:
   8 * https://bugs.libre-soc.org/show_bug.cgi?id=348
   9 * https://libre-soc.org/openpower/isa/sprset/
  10 """
  11
  12 from nmigen import Signal, Const
  13 from ieee754.fpcommon.getop import FPPipeContext
  14 from soc.fu.pipe_data import IntegerData
  15 from soc.decoder.power_decoder2 import Data
  16 from soc.fu.spr.spr_input_record import CompSPROpSubset
  17
  18
  19 class SPRInputData(IntegerData):
  20     regspec = [('INT', 'ra', '0:63'),
  21                ('SPR', 'spr1', '0:63'),
  22                ('FAST', 'spr2', '0:63'),
  23                ('XER', 'xer_so', '32'),
  24                ('XER', 'xer_ov', '33,44'),
  25                ('XER', 'xer_ca', '34,45')]
  26     def __init__(self, pspec):
  27         super().__init__(pspec)
  28         self.ra = Signal(64, reset_less=True) # RA
  29         self.spr1 = Signal(64, reset_less=True) # SPR (slow)
  30         self.spr2 = Signal(64, reset_less=True) # SPR (fast: MSR, LR, CTR etc)
  31         self.xer_so = Signal(reset_less=True) # XER bit 32: SO
  32         self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
  33         self.xer_ov = Signal(2, reset_less=True) # bit0: ov, bit1: ov32
  34         # convenience
  35         self.a = self.ra
  36
  37     def __iter__(self):
  38         yield from super().__iter__()
  39         yield self.ra
  40         yield self.spr1
  41         yield self.spr2
  42         yield self.xer_ca
  43         yield self.xer_ov
  44         yield self.xer_so
  45
  46     def eq(self, i):
  47         lst = super().eq(i)
  48         return lst + [self.ra.eq(i.ra), self.reg.eq(i.reg),
  49                       self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
  50                       self.xer_ca.eq(i.xer_ca),
  51                       self.xer_ov.eq(i.xer_ov),
  52                       self.xer_so.eq(i.xer_so)]
  53
  54
  55 class SPROutputData(IntegerData):
  56     regspec = [('INT', 'o', '0:63'),
  57                ('SPR', 'spr1', '0:63'),
  58                ('FAST', 'spr2', '0:63'),
  59                ('XER', 'xer_so', '32'),
  60                ('XER', 'xer_ov', '33,44'),
  61                ('XER', 'xer_ca', '34,45')]
  62     def __init__(self, pspec):
  63         super().__init__(pspec)
  64         self.o = Data(64, name="rt") # RT
  65         self.spr1 = Data(64, name="spr1") # SPR (slow)
  66         self.spr2 = Data(64, name="spr2") # SPR (fast: MSR, LR, CTR etc)
  67         self.xer_so = Data(1, name="xer_so") # XER bit 32: SO
  68         self.xer_ca = Data(2, name="xer_ca") # XER bit 34/45: CA/CA32
  69         self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32
  70
  71     def __iter__(self):
  72         yield from super().__iter__()
  73         yield self.o
  74         yield self.spr1
  75         yield self.spr2
  76         yield self.xer_ca
  77         yield self.xer_ov
  78         yield self.xer_so
  79
  80     def eq(self, i):
  81         lst = super().eq(i)
  82         return lst + [self.o.eq(i.o), self.reg.eq(i.reg),
  83                       self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
  84                       self.xer_ca.eq(i.xer_ca),
  85                       self.xer_ov.eq(i.xer_ov),
  86                       self.xer_so.eq(i.xer_so)]
  87
  88
  89
  90 class SPRPipeSpec:
  91     regspec = (SPRInputData.regspec, SPROutputData.regspec)
  92     opsubsetkls = CompSPROpSubset
  93     def __init__(self, id_wid, op_wid):
  94         self.id_wid = id_wid
  95         self.op_wid = op_wid
  96         self.opkls = lambda _: self.opsubsetkls(name="op")
  97         self.stage = None
  98         self.pipekls = SimpleHandshakeRedir