src/soc/litex/florent/README.txt

   1 # sim openocd test
   2
   3 create verilog file "python issuer_verilog libresoc.v"
   4 copy to libresoc/ directory
   5 terminal 1: ./sim.py
   6 terminal 2: openocd -f openocd.cfg -c init -c 'svf idcode_test2.svf'
   7
   8 # ecp5 build
   9
  10 ./versa_ecp5.py --sys-clk-freq=55e6 --build
  11 ./versa_ecp5.py --sys-clk-freq=55e6 --load