src/soc/litex/florent/libresoc/core.py

   1 import os
   2
   3 from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
   4
   5 from litex.soc.interconnect import wishbone as wb
   6 from litex.soc.cores.cpu import CPU
   7
   8
   9 from libresoc.ls180io import make_uart, make_gpio
  10 from litex.build.generic_platform import ConstraintManager
  11
  12
  13 CPU_VARIANTS = ["standard", "standard32", "standardjtag", "ls180"]
  14
  15
  16 def make_wb_bus(prefix, obj, simple=False):
  17     res = {}
  18     outpins = ['stb', 'cyc', 'we', 'adr', 'dat_w', 'sel']
  19     if not simple:
  20         outpins += ['cti', 'bte']
  21     for o in outpins:
  22         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
  23     for i in ['ack', 'err', 'dat_r']:
  24         res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
  25     return res
  26
  27 def make_wb_slave(prefix, obj):
  28     res = {}
  29     for i in ['stb', 'cyc', 'cti', 'bte', 'we', 'adr', 'dat_w', 'sel']:
  30         res['i_%s__%s' % (prefix, i)] = getattr(obj, i)
  31     for o in ['ack', 'err', 'dat_r']:
  32         res['o_%s__%s' % (prefix, o)] = getattr(obj, o)
  33     return res
  34
  35 class LibreSoC(CPU):
  36     name                 = "libre_soc"
  37     human_name           = "Libre-SoC"
  38     variants             = CPU_VARIANTS
  39     endianness           = "little"
  40     gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
  41     linker_output_format = "elf64-powerpcle"
  42     nop                  = "nop"
  43     io_regions           = {0xc0000000: 0x10000000} # origin, length
  44
  45     @property
  46     def mem_map(self):
  47         return {"csr": 0xc0000000}
  48
  49     @property
  50     def gcc_flags(self):
  51         flags  = "-m64 "
  52         flags += "-mabi=elfv2 "
  53         flags += "-msoft-float "
  54         flags += "-mno-string "
  55         flags += "-mno-multiple "
  56         flags += "-mno-vsx "
  57         flags += "-mno-altivec "
  58         flags += "-mlittle-endian "
  59         flags += "-mstrict-align "
  60         flags += "-fno-stack-protector "
  61         flags += "-mcmodel=small "
  62         flags += "-D__microwatt__ "
  63         return flags
  64
  65     def __init__(self, platform, variant="standard"):
  66         self.platform     = platform
  67         self.variant      = variant
  68         self.reset        = Signal()
  69         self.interrupt    = Signal(16)
  70
  71         if variant == "standard32":
  72             self.data_width           = 32
  73             self.dbus = dbus = wb.Interface(data_width=32, adr_width=30)
  74         else:
  75             self.dbus = dbus = wb.Interface(data_width=64, adr_width=29)
  76             self.data_width           = 64
  77         self.ibus = ibus = wb.Interface(data_width=64, adr_width=29)
  78
  79         self.xics_icp = icp = wb.Interface(data_width=32, adr_width=30)
  80         self.xics_ics = ics = wb.Interface(data_width=32, adr_width=30)
  81
  82         jtag_en = ('jtag' in variant) or variant == 'ls180'
  83
  84         if variant != "ls180":
  85             self.simple_gpio = gpio = wb.Interface(data_width=32, adr_width=30)
  86         if jtag_en:
  87             self.jtag_wb = jtag_wb = wb.Interface(data_width=64, adr_width=29)
  88
  89         self.periph_buses = [ibus, dbus]
  90         self.memory_buses = []
  91
  92         if jtag_en:
  93             self.periph_buses.append(jtag_wb)
  94             self.jtag_tck = Signal(1)
  95             self.jtag_tms = Signal(1)
  96             self.jtag_tdi = Signal(1)
  97             self.jtag_tdo = Signal(1)
  98         else:
  99             self.dmi_addr = Signal(4)
 100             self.dmi_din = Signal(64)
 101             self.dmi_dout = Signal(64)
 102             self.dmi_wr = Signal(1)
 103             self.dmi_ack = Signal(1)
 104             self.dmi_req = Signal(1)
 105
 106         # # #
 107
 108         self.cpu_params = dict(
 109             # Clock / Reset
 110             i_clk              = ClockSignal(),
 111             i_rst              = ResetSignal() | self.reset,
 112
 113             # Monitoring / Debugging
 114             i_pc_i             = 0,
 115             i_pc_i_ok          = 0,
 116             i_core_bigendian_i = 0, # Signal(),
 117             o_busy_o           = Signal(),   # not connected
 118             o_memerr_o         = Signal(),   # not connected
 119             o_pc_o             = Signal(64), # not connected
 120
 121             # interrupts
 122             i_int_level_i      = self.interrupt,
 123
 124         )
 125
 126         if jtag_en:
 127             self.cpu_params.update(dict(
 128                 # JTAG Debug bus
 129                 o_TAP_bus__tdo = self.jtag_tdo,
 130                 i_TAP_bus__tdi = self.jtag_tdi,
 131                 i_TAP_bus__tms = self.jtag_tms,
 132                 i_TAP_bus__tck = self.jtag_tck,
 133             ))
 134         else:
 135             self.cpu_params.update(dict(
 136                 # DMI Debug bus
 137                 i_dmi_addr_i          = self.dmi_addr,
 138                 i_dmi_din             = self.dmi_din,
 139                 o_dmi_dout            = self.dmi_dout,
 140                 i_dmi_req_i           = self.dmi_req,
 141                 i_dmi_we_i            = self.dmi_wr,
 142                 o_dmi_ack_o           = self.dmi_ack,
 143             ))
 144
 145         # add clock select, pll output
 146         if variant == "ls180":
 147             self.pll_48_o = Signal()
 148             self.clk_sel = Signal(3)
 149             self.cpu_params['i_clk_sel_i'] = self.clk_sel
 150             self.cpu_params['o_pll_48_o'] = self.pll_48_o
 151
 152         # add wishbone buses to cpu params
 153         self.cpu_params.update(make_wb_bus("ibus", ibus))
 154         self.cpu_params.update(make_wb_bus("dbus", dbus))
 155         self.cpu_params.update(make_wb_slave("ics_wb", ics))
 156         self.cpu_params.update(make_wb_slave("icp_wb", icp))
 157         if variant != "ls180":
 158             self.cpu_params.update(make_wb_slave("gpio_wb", gpio))
 159         if jtag_en:
 160             self.cpu_params.update(make_wb_bus("jtag_wb", jtag_wb, simple=True))
 161
 162         # add verilog sources
 163         self.add_sources(platform)
 164
 165     def set_reset_address(self, reset_address):
 166         assert not hasattr(self, "reset_address")
 167         self.reset_address = reset_address
 168         assert reset_address == 0x00000000
 169
 170     @staticmethod
 171     def add_sources(platform):
 172         cdir = os.path.dirname(__file__)
 173         platform.add_source(os.path.join(cdir, "libresoc.v"))
 174
 175     def do_finalize(self):
 176         self.specials += Instance("test_issuer", **self.cpu_params)
 177