src/soc/scoreboard/reg_select.py

   1 # (DO NOT REMOVE THESE NOTICES)
   2 # SPDX-License-Identifier: LGPLv3+
   3 # Copyright (C) 2019, 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   4 # Part of the Libre-SOC Project.
   5 # Sponsored by NLnet       EU Grant No: 825310 and 825322
   6 # Sponsored by NGI POINTER EU Grant No: 871528
   7
   8 from nmigen.cli import verilog, rtlil
   9 from nmigen import Elaboratable, Module, Signal
  10
  11
  12 class Reg_Rsv(Elaboratable):
  13     """ these are allocated per-Register (vertically),
  14         and are each of length fu_count
  15     """
  16     def __init__(self, fu_count, n_src, n_dst):
  17         self.n_src = n_src
  18         self.n_dst = n_dst
  19         self.fu_count = fu_count
  20         self.dst_rsel_i = tuple(Signal(fu_count, name="dst%i_rsel_i" % (i+1),
  21                                        reset_less=True) \
  22                                 for i in range(n_dst))
  23         self.src_rsel_i = tuple(Signal(fu_count, name="src%i_rsel_i" % (i+1),
  24                                        reset_less=True) \
  25                                 for i in range(n_src))
  26         self.dst_rsel_o = Signal(n_dst, reset_less=True)
  27         self.src_rsel_o = Signal(n_src, reset_less=True)
  28
  29     def elaborate(self, platform):
  30         m = Module()
  31         for i in range(self.n_dst):
  32             m.d.comb += self.dst_rsel_o[i].eq(self.dst_rsel_i[i].bool())
  33         for i in range(self.n_src):
  34             m.d.comb += self.src_rsel_o[i].eq(self.src_rsel_i[i].bool())
  35         return m
  36
  37     def __iter__(self):
  38         yield from self.dst_rsel_i
  39         yield from self.src_rsel_i
  40         yield self.dst_rsel_o
  41         yield self.src_rsel_o
  42
  43     def ports(self):
  44         return list(self)
  45
  46
  47 def test_reg_rsv():
  48     dut = Reg_Rsv(4, 2, 2)
  49     vl = rtlil.convert(dut, ports=dut.ports())
  50     with open("test_reg_rsv.il", "w") as f:
  51         f.write(vl)
  52
  53
  54 if __name__ == '__main__':
  55     test_reg_rsv()