src/soc/scoremulti/fu_fu_matrix.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable, Array, Cat, Const
   4
   5 from soc.scoremulti.fu_dep_cell import FUDependenceCell
   6 from soc.scoreboard.fu_picker_vec import FU_Pick_Vec
   7
   8 """
   9
  10  6600 Function Unit Dependency Table Matrix inputs / outputs
  11  -----------------------------------------------------------
  12
  13 """
  14
  15 class FUFUDepMatrix(Elaboratable):
  16     """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
  17     """
  18     def __init__(self, n_fu_row, n_fu_col, n_src, n_dest):
  19         self.n_fu_row = n_fu_row                  # Y (FU row#)   ^v
  20         self.n_fu_col = n_fu_col                # X (FU col #)  <>
  21         self.n_src = n_src
  22         self.n_dest = n_dest
  23         self.rd_pend_i = Signal(n_fu_row, reset_less=True) # Rd pending (left)
  24         self.wr_pend_i = Signal(n_fu_row, reset_less=True) # Wr pending (left)
  25         self.issue_i = Signal(n_fu_col, reset_less=True)    # Issue in (top)
  26
  27         self.go_die_i = Signal(n_fu_row, reset_less=True) # Go Die in (left)
  28         # set up go_wr and go_wr array
  29         rd = []
  30         for i in range(n_src):
  31             j = i + 1 # name numbering to match src1/src2
  32             rd.append(Signal(n_fu_row, name="gord%d_i" % j, reset_less=True))
  33         wr = []
  34         for i in range(n_src):
  35             j = i + 1 # name numbering to match src1/src2
  36             wr.append(Signal(n_fu_row, name="gowr%d_i" % j, reset_less=True))
  37
  38         self.go_wr_i = Array(wr)  # Go Write in (left)
  39         self.go_rd_i = Array(rd)  # Go Read in (left)
  40
  41         # for Function Unit Readable/Writable (horizontal)
  42         self.readable_o = Signal(n_fu_col, reset_less=True) # readable (bot)
  43         self.writable_o = Signal(n_fu_col, reset_less=True) # writable (bot)
  44
  45     def elaborate(self, platform):
  46         m = Module()
  47
  48         # ---
  49         # matrix of dependency cells
  50         # ---
  51         dm = Array(FUDependenceCell(f, self.n_fu_col, self.n_src, self.n_dest) \
  52                                             for f in range(self.n_fu_row))
  53         for y in range(self.n_fu_row):
  54                 setattr(m.submodules, "dm%d" % y, dm[y])
  55
  56         # ---
  57         # array of Function Unit Readable/Writable: row-length, horizontal
  58         # ---
  59         fur = Array(FU_Pick_Vec(self.n_fu_row) for r in range(self.n_fu_col))
  60         for x in range(self.n_fu_col):
  61             setattr(m.submodules, "fur_x%d" % (x), fur[x])
  62
  63         # ---
  64         # connect FU Readable/Writable vector
  65         # ---
  66         readable = []
  67         writable = []
  68         for y in range(self.n_fu_row):
  69             fu = fur[y]
  70             # accumulate Readable/Writable Vector outputs
  71             readable.append(fu.readable_o)
  72             writable.append(fu.writable_o)
  73
  74         # ... and output them from this module (horizontal, width=REGs)
  75         m.d.comb += self.readable_o.eq(Cat(*readable))
  76         m.d.comb += self.writable_o.eq(Cat(*writable))
  77
  78         # ---
  79         # connect FU Pending
  80         # ---
  81         for y in range(self.n_fu_row):
  82             dc = dm[y]
  83             fu = fur[y]
  84             # connect cell reg-select outputs to Reg Vector In
  85             m.d.comb += [fu.rd_pend_i.eq(dc.rd_wait_o),
  86                          fu.wr_pend_i.eq(dc.wr_wait_o),
  87                         ]
  88
  89         # ---
  90         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
  91         # ---
  92         for x in range(self.n_fu_col):
  93             issue_i = []
  94             for y in range(self.n_fu_row):
  95                 dc = dm[y]
  96                 # accumulate cell inputs issue
  97                 issue_i.append(dc.issue_i[x])
  98             # wire up inputs from module to row cell inputs
  99             m.d.comb += Cat(*issue_i).eq(self.issue_i)
 100
 101         # ---
 102         # connect Matrix go_rd_i/go_wr_i to module readable/writable
 103         # ---
 104         for y in range(self.n_fu_row):
 105             dc = dm[y]
 106             # wire up inputs from module to row cell inputs
 107             m.d.comb += dc.go_die_i.eq(self.go_die_i)
 108             for i in range(self.n_src):
 109                 m.d.comb += dc.go_rd_i[i].eq(self.go_rd_i[i])
 110             for i in range(self.n_dest):
 111                 m.d.comb += dc.go_wr_i[i].eq(self.go_wr_i[i])
 112
 113         # ---
 114         # connect Matrix pending
 115         # ---
 116         for y in range(self.n_fu_row):
 117             dc = dm[y]
 118             # wire up inputs from module to row cell inputs
 119             m.d.comb += [dc.rd_pend_i.eq(self.rd_pend_i),
 120                          dc.wr_pend_i.eq(self.wr_pend_i),
 121                         ]
 122
 123         return m
 124
 125     def __iter__(self):
 126         yield self.rd_pend_i
 127         yield self.wr_pend_i
 128         yield self.issue_i
 129         yield self.go_die_i
 130         yield from self.go_wr_i
 131         yield from self.go_rd_i
 132         yield self.readable_o
 133         yield self.writable_o
 134
 135     def ports(self):
 136         return list(self)
 137
 138 def d_matrix_sim(dut):
 139     """ XXX TODO
 140     """
 141     yield dut.dest_i.eq(1)
 142     yield dut.issue_i.eq(1)
 143     yield
 144     yield dut.issue_i.eq(0)
 145     yield
 146     yield dut.src1_i.eq(1)
 147     yield dut.issue_i.eq(1)
 148     yield
 149     yield dut.issue_i.eq(0)
 150     yield
 151     yield dut.go_rd_i.eq(1)
 152     yield
 153     yield dut.go_rd_i.eq(0)
 154     yield
 155     yield dut.go_wr_i.eq(1)
 156     yield
 157     yield dut.go_wr_i.eq(0)
 158     yield
 159
 160 def test_fu_fu_matrix():
 161     dut = FUFUDepMatrix(n_fu_row=30, n_fu_col=30, n_src=3, n_dest=2)
 162     vl = rtlil.convert(dut, ports=dut.ports())
 163     with open("test_fu_fu_matrix.il", "w") as f:
 164         f.write(vl)
 165
 166     run_simulation(dut, d_matrix_sim(dut), vcd_name='test_fu_fu_matrix.vcd')
 167
 168 if __name__ == '__main__':
 169     test_fu_fu_matrix()