3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
20 (update: actually this is being added now:
21 https://bugs.libre-soc.org/show_bug.cgi?id=737)
24 from nmigen
import (Elaboratable
, Module
, Signal
, ResetSignal
, Cat
, Mux
,
26 from nmigen
.cli
import rtlil
28 from openpower
.decoder
.power_decoder2
import PowerDecodeSubset
29 from openpower
.decoder
.power_regspec_map
import regspec_decode
30 from openpower
.sv
.svp64
import SVP64Rec
32 from nmutil
.picker
import PriorityPicker
33 from nmutil
.util
import treereduce
34 from nmutil
.singlepipe
import ControlBase
36 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
, LDSTFunctionUnit
37 from soc
.regfile
.regfiles
import RegFiles
38 from openpower
.decoder
.power_decoder2
import get_rdflags
39 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
40 from soc
.config
.test
.test_loadstore
import TestMemPspec
41 from openpower
.decoder
.power_enums
import MicrOp
, Function
42 from soc
.simple
.core_data
import CoreInput
, CoreOutput
44 from collections
import defaultdict
, namedtuple
47 from nmutil
.util
import rising_edge
49 FUSpec
= namedtuple("FUSpec", ["funame", "fu", "idx"])
50 ByRegSpec
= namedtuple("ByRegSpec", ["okflag", "regport", "wid", "specs"])
52 # helper function for reducing a list of signals down to a parallel
54 def ortreereduce(tree
, attr
="o_data"):
55 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
58 def ortreereduce_sig(tree
):
59 return treereduce(tree
, operator
.or_
, lambda x
: x
)
62 # helper function to place full regs declarations first
63 def sort_fuspecs(fuspecs
):
65 for (regname
, fspec
) in fuspecs
.items():
66 if regname
.startswith("full"):
67 res
.append((regname
, fspec
))
68 for (regname
, fspec
) in fuspecs
.items():
69 if not regname
.startswith("full"):
70 res
.append((regname
, fspec
))
71 return res
# enumerate(res)
74 # derive from ControlBase rather than have a separate Stage instance,
75 # this is simpler to do
76 class NonProductionCore(ControlBase
):
77 def __init__(self
, pspec
):
80 # test is SVP64 is to be enabled
81 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
83 # test to see if regfile ports should be reduced
84 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
85 (pspec
.regreduce
== True))
87 # test to see if overlapping of instructions is allowed
88 # (not normally enabled for TestIssuer FSM but useful for checking
89 # the bitvector hazard detection, before doing In-Order)
90 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
91 (pspec
.allow_overlap
== True))
94 self
.make_hazard_vecs
= self
.allow_overlap
95 self
.core_type
= "fsm"
96 if hasattr(pspec
, "core_type"):
97 self
.core_type
= pspec
.core_type
99 super().__init
__(stage
=self
)
101 # single LD/ST funnel for memory access
102 self
.l0
= l0
= TstL0CacheBuffer(pspec
, n_units
=1)
105 # function units (only one each)
106 # only include mmu if enabled in pspec
107 self
.fus
= AllFunctionUnits(pspec
, pilist
=[pi
])
109 # link LoadStore1 into MMU
110 mmu
= self
.fus
.get_fu('mmu0')
111 print ("core pspec", pspec
.ldst_ifacetype
)
112 print ("core mmu", mmu
)
114 print ("core lsmem.lsi", l0
.cmpi
.lsmem
.lsi
)
115 mmu
.alu
.set_ldst_interface(l0
.cmpi
.lsmem
.lsi
)
117 # register files (yes plural)
118 self
.regs
= RegFiles(pspec
, make_hazard_vecs
=self
.make_hazard_vecs
)
120 # set up input and output: unusual requirement to set data directly
121 # (due to the way that the core is set up in a different domain,
122 # see TestIssuer.setup_peripherals
123 self
.p
.i_data
, self
.n
.o_data
= self
.new_specs(None)
124 self
.i
, self
.o
= self
.p
.i_data
, self
.n
.o_data
126 # actual internal input data used (captured)
127 self
.ireg
= self
.ispec()
129 # create per-FU instruction decoders (subsetted). these "satellite"
130 # decoders reduce wire fan-out from the one (main) PowerDecoder2
131 # (used directly by the trap unit) to the *twelve* (or more)
132 # Function Units. we can either have 32 wires (the instruction)
133 # to each, or we can have well over a 200 wire fan-out (to 12
134 # ALUs). it's an easy choice to make.
138 # eep, these should be *per FU* i.e. for FunctionUnitBaseMulti
139 # they should be shared (put into the ALU *once*).
141 for funame
, fu
in self
.fus
.fus
.items():
142 f_name
= fu
.fnunit
.name
143 fnunit
= fu
.fnunit
.value
144 opkls
= fu
.opsubsetkls
146 # TRAP decoder is the *main* decoder
147 self
.trapunit
= funame
149 assert funame
not in self
.decoders
150 self
.decoders
[funame
] = PowerDecodeSubset(None, opkls
, f_name
,
152 state
=self
.ireg
.state
,
153 svp64_en
=self
.svp64_en
,
154 regreduce_en
=self
.regreduce_en
)
155 self
.des
[funame
] = self
.decoders
[funame
].do
157 # create per-Function Unit write-after-write hazard signals
158 # yes, really, this should have been added in ReservationStations
160 for funame
, fu
in self
.fus
.fus
.items():
161 fu
._waw
_hazard
= Signal(name
="waw_%s" % funame
)
163 # share the SPR decoder with the MMU if it exists
164 if "mmu0" in self
.decoders
:
165 self
.decoders
["mmu0"].mmu0_spr_dec
= self
.decoders
["spr0"]
167 # next 3 functions are Stage API Compliance
168 def setup(self
, m
, i
):
172 return CoreInput(self
.pspec
, self
.svp64_en
, self
.regreduce_en
)
177 # elaborate function to create HDL
178 def elaborate(self
, platform
):
179 m
= super().elaborate(platform
)
181 # for testing purposes, to cut down on build time in coriolis2
182 if hasattr(self
.pspec
, "nocore") and self
.pspec
.nocore
== True:
183 x
= Signal() # dummy signal
188 m
.submodules
.fus
= self
.fus
189 m
.submodules
.l0
= l0
= self
.l0
190 self
.regs
.elaborate_into(m
, platform
)
194 # amalgamate write-hazards into a single top-level Signal
195 self
.waw_hazard
= Signal()
197 for funame
, fu
in self
.fus
.fus
.items():
198 whaz
.append(fu
._waw
_hazard
)
199 comb
+= self
.waw_hazard
.eq(Cat(*whaz
).bool())
202 self
.connect_satellite_decoders(m
)
204 # ssh, cheat: trap uses the main decoder because of the rewriting
205 self
.des
[self
.trapunit
] = self
.ireg
.e
.do
207 # connect up Function Units, then read/write ports, and hazard conflict
208 self
.issue_conflict
= Signal()
209 fu_bitdict
, fu_selected
= self
.connect_instruction(m
)
210 raw_hazard
= self
.connect_rdports(m
, fu_bitdict
, fu_selected
)
211 self
.connect_wrports(m
, fu_bitdict
, fu_selected
)
212 if self
.allow_overlap
:
213 comb
+= self
.issue_conflict
.eq(raw_hazard
)
215 # note if an exception happened. in a pipelined or OoO design
216 # this needs to be accompanied by "shadowing" (or stalling)
218 for exc
in self
.fus
.excs
.values():
219 el
.append(exc
.happened
)
220 if len(el
) > 0: # at least one exception
221 comb
+= self
.o
.exc_happened
.eq(Cat(*el
).bool())
225 def connect_satellite_decoders(self
, m
):
227 for k
, v
in self
.decoders
.items():
228 # connect each satellite decoder and give it the instruction.
229 # as subset decoders this massively reduces wire fanout given
230 # the large number of ALUs
231 m
.submodules
["dec_%s" % k
] = v
232 comb
+= v
.dec
.raw_opcode_in
.eq(self
.ireg
.raw_insn_i
)
233 comb
+= v
.dec
.bigendian
.eq(self
.ireg
.bigendian_i
)
234 # sigh due to SVP64 RA_OR_ZERO detection connect these too
235 comb
+= v
.sv_a_nz
.eq(self
.ireg
.sv_a_nz
)
236 if not self
.svp64_en
:
238 comb
+= v
.pred_sm
.eq(self
.ireg
.sv_pred_sm
)
239 comb
+= v
.pred_dm
.eq(self
.ireg
.sv_pred_dm
)
240 if k
== self
.trapunit
:
242 comb
+= v
.sv_rm
.eq(self
.ireg
.sv_rm
) # pass through SVP64 RM
243 comb
+= v
.is_svp64_mode
.eq(self
.ireg
.is_svp64_mode
)
244 # only the LDST PowerDecodeSubset *actually* needs to
245 # know to use the alternative decoder. this is all
247 if not k
.lower().startswith("ldst"):
249 comb
+= v
.use_svp64_ldst_dec
.eq( self
.ireg
.use_svp64_ldst_dec
)
251 def connect_instruction(self
, m
):
252 """connect_instruction
254 uses decoded (from PowerOp) function unit information from CSV files
255 to ascertain which Function Unit should deal with the current
258 some (such as OP_ATTN, OP_NOP) are dealt with here, including
259 ignoring it and halting the processor. OP_NOP is a bit annoying
260 because the issuer expects busy flag still to be raised then lowered.
261 (this requires a fake counter to be set).
263 comb
, sync
= m
.d
.comb
, m
.d
.sync
266 # indicate if core is busy
267 busy_o
= self
.o
.busy_o
268 any_busy_o
= self
.o
.any_busy_o
270 # connect up temporary copy of incoming instruction. the FSM will
271 # either blat the incoming instruction (if valid) into self.ireg
272 # or if the instruction could not be delivered, keep dropping the
273 # latched copy into ireg
274 ilatch
= self
.ispec()
275 self
.instr_active
= Signal()
277 # enable/busy-signals for each FU, get one bit for each FU (by name)
278 fu_enable
= Signal(len(fus
), reset_less
=True)
279 fu_busy
= Signal(len(fus
), reset_less
=True)
282 for i
, funame
in enumerate(fus
.keys()):
283 fu_bitdict
[funame
] = fu_enable
[i
]
284 fu_selected
[funame
] = fu_busy
[i
]
286 # identify function units and create a list by fnunit so that
287 # PriorityPickers can be created for selecting one of them that
288 # isn't busy at the time the incoming instruction needs passing on
289 by_fnunit
= defaultdict(list)
290 for fname
, member
in Function
.__members
__.items():
291 for funame
, fu
in fus
.items():
292 fnunit
= fu
.fnunit
.value
293 if member
.value
& fnunit
: # this FU handles this type of op
294 by_fnunit
[fname
].append((funame
, fu
)) # add by Function
296 # ok now just print out the list of FUs by Function, because we can
297 for fname
, fu_list
in by_fnunit
.items():
298 print ("FUs by type", fname
, fu_list
)
300 # now create a PriorityPicker per FU-type such that only one
301 # non-busy FU will be picked
303 fu_found
= Signal() # take a note if no Function Unit was available
304 for fname
, fu_list
in by_fnunit
.items():
305 i_pp
= PriorityPicker(len(fu_list
))
306 m
.submodules
['i_pp_%s' % fname
] = i_pp
308 for i
, (funame
, fu
) in enumerate(fu_list
):
309 # match the decoded instruction (e.do.fn_unit) against the
310 # "capability" of this FU, gate that by whether that FU is
311 # busy, and drop that into the PriorityPicker.
312 # this will give us an output of the first available *non-busy*
313 # Function Unit (Reservation Statio) capable of handling this
315 fnunit
= fu
.fnunit
.value
316 en_req
= Signal(name
="issue_en_%s" % funame
, reset_less
=True)
317 fnmatch
= (self
.ireg
.e
.do
.fn_unit
& fnunit
).bool()
318 comb
+= en_req
.eq(fnmatch
& ~fu
.busy_o
&
320 i_l
.append(en_req
) # store in list for doing the Cat-trick
321 # picker output, gated by enable: store in fu_bitdict
322 po
= Signal(name
="o_issue_pick_"+funame
) # picker output
323 comb
+= po
.eq(i_pp
.o
[i
] & i_pp
.en_o
)
324 comb
+= fu_bitdict
[funame
].eq(po
)
325 comb
+= fu_selected
[funame
].eq(fu
.busy_o | po
)
326 # if we don't do this, then when there are no FUs available,
327 # the "p.o_ready" signal will go back "ok we accepted this
328 # instruction" which of course isn't true.
329 with m
.If(i_pp
.en_o
):
330 comb
+= fu_found
.eq(1)
331 # for each input, Cat them together and drop them into the picker
332 comb
+= i_pp
.i
.eq(Cat(*i_l
))
334 # rdmask, which is for registers needs to come from the *main* decoder
335 for funame
, fu
in fus
.items():
336 rdmask
= get_rdflags(self
.ireg
.e
, fu
)
337 comb
+= fu
.rdmaskn
.eq(~rdmask
)
339 # sigh - need a NOP counter
341 with m
.If(counter
!= 0):
342 sync
+= counter
.eq(counter
- 1)
345 # default to reading from incoming instruction: may be overridden
346 # by copy from latch when "waiting"
347 comb
+= self
.ireg
.eq(self
.i
)
348 # always say "ready" except if overridden
349 comb
+= self
.p
.o_ready
.eq(1)
352 with m
.State("READY"):
353 with m
.If(self
.p
.i_valid
): # run only when valid
354 with m
.Switch(self
.ireg
.e
.do
.insn_type
):
355 # check for ATTN: halt if true
356 with m
.Case(MicrOp
.OP_ATTN
):
357 m
.d
.sync
+= self
.o
.core_terminate_o
.eq(1)
359 # fake NOP - this isn't really used (Issuer detects NOP)
360 with m
.Case(MicrOp
.OP_NOP
):
361 sync
+= counter
.eq(2)
365 comb
+= self
.instr_active
.eq(1)
366 comb
+= self
.p
.o_ready
.eq(0)
367 # connect instructions. only one enabled at a time
368 for funame
, fu
in fus
.items():
369 do
= self
.des
[funame
]
370 enable
= fu_bitdict
[funame
]
372 # run this FunctionUnit if enabled route op,
373 # issue, busy, read flags and mask to FU
375 # operand comes from the *local* decoder
376 # do not actually issue, though, if there
377 # is a waw hazard. decoder has to still
378 # be asserted in order to detect that, tho
379 comb
+= fu
.oper_i
.eq_from(do
)
380 # issue when valid (and no write-hazard)
381 comb
+= fu
.issue_i
.eq(~self
.waw_hazard
)
382 # instruction ok, indicate ready
383 comb
+= self
.p
.o_ready
.eq(1)
385 if self
.allow_overlap
:
386 with m
.If(~fu_found | self
.waw_hazard
):
387 # latch copy of instruction
388 sync
+= ilatch
.eq(self
.i
)
389 comb
+= self
.p
.o_ready
.eq(1) # accept
393 with m
.State("WAITING"):
394 comb
+= self
.instr_active
.eq(1)
395 comb
+= self
.p
.o_ready
.eq(0)
397 # using copy of instruction, keep waiting until an FU is free
398 comb
+= self
.ireg
.eq(ilatch
)
399 with m
.If(fu_found
): # wait for conflict to clear
400 # connect instructions. only one enabled at a time
401 for funame
, fu
in fus
.items():
402 do
= self
.des
[funame
]
403 enable
= fu_bitdict
[funame
]
405 # run this FunctionUnit if enabled route op,
406 # issue, busy, read flags and mask to FU
408 # operand comes from the *local* decoder,
409 # which is asserted even if not issued,
410 # so that WaW-detection can check for hazards.
411 # only if the waw hazard is clear does the
412 # instruction actually get issued
413 comb
+= fu
.oper_i
.eq_from(do
)
415 comb
+= fu
.issue_i
.eq(~self
.waw_hazard
)
416 with m
.If(~self
.waw_hazard
):
417 comb
+= self
.p
.o_ready
.eq(1)
421 print ("core: overlap allowed", self
.allow_overlap
)
422 # true when any FU is busy (including the cycle where it is perhaps
423 # to be issued - because that's what fu_busy is)
424 comb
+= any_busy_o
.eq(fu_busy
.bool())
425 if not self
.allow_overlap
:
426 # for simple non-overlap, if any instruction is busy, set
427 # busy output for core.
428 comb
+= busy_o
.eq(any_busy_o
)
430 # sigh deal with a fun situation that needs to be investigated
432 with m
.If(self
.issue_conflict
):
434 # make sure that LDST, SPR, MMU, Branch and Trap all say "busy"
435 # and do not allow overlap. these are all the ones that
436 # are non-forward-progressing: exceptions etc. that otherwise
437 # change CoreState for some reason (MSR, PC, SVSTATE)
438 for funame
, fu
in fus
.items():
439 if (funame
.lower().startswith('ldst') or
440 funame
.lower().startswith('branch') or
441 funame
.lower().startswith('mmu') or
442 funame
.lower().startswith('spr') or
443 funame
.lower().startswith('trap')):
444 with m
.If(fu
.busy_o
):
447 # return both the function unit "enable" dict as well as the "busy".
448 # the "busy-or-issued" can be passed in to the Read/Write port
449 # connecters to give them permission to request access to regfiles
450 return fu_bitdict
, fu_selected
452 def connect_rdport(self
, m
, fu_bitdict
, fu_selected
,
453 rdpickers
, regfile
, regname
, fspec
):
454 comb
, sync
= m
.d
.comb
, m
.d
.sync
460 # select the required read port. these are pre-defined sizes
461 rfile
= regs
.rf
[regfile
.lower()]
462 rport
= rfile
.r_ports
[rpidx
]
463 print("read regfile", rpidx
, regfile
, regs
.rf
.keys(),
466 # for checking if the read port has an outstanding write
467 if self
.make_hazard_vecs
:
468 wv
= regs
.wv
[regfile
.lower()]
469 wvchk
= wv
.q_int
# write-vec bit-level hazard check
471 # if a hazard is detected on this read port, simply blithely block
472 # every FU from reading on it. this is complete overkill but very
474 hazard_detected
= Signal(name
="raw_%s_%s" % (regfile
, rpidx
))
477 if not isinstance(fspecs
, list):
483 for i
, fspec
in enumerate(fspecs
):
484 # get the regfile specs for this regfile port
485 print ("fpsec", i
, fspec
, len(fspec
.specs
))
486 name
= "%s_%s_%d" % (regfile
, regname
, i
)
487 ppoffs
.append(pplen
) # record offset for picker
488 pplen
+= len(fspec
.specs
)
489 rdflag
= Signal(name
="rdflag_"+name
, reset_less
=True)
490 comb
+= rdflag
.eq(fspec
.okflag
)
491 rdflags
.append(rdflag
)
493 print ("pplen", pplen
)
495 # create a priority picker to manage this port
496 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(pplen
)
497 m
.submodules
["rdpick_%s_%s" % (regfile
, rpidx
)] = rdpick
503 for i
, fspec
in enumerate(fspecs
):
504 (rf
, _read
, wid
, fuspecs
) = \
505 (fspec
.okflag
, fspec
.regport
, fspec
.wid
, fspec
.specs
)
506 # connect up the FU req/go signals, and the reg-read to the FU
507 # and create a Read Broadcast Bus
508 for pi
, fuspec
in enumerate(fspec
.specs
):
509 (funame
, fu
, idx
) = (fuspec
.funame
, fuspec
.fu
, fuspec
.idx
)
511 name
= "%s_%s_%s_%i" % (regfile
, rpidx
, funame
, pi
)
512 fu_active
= fu_selected
[funame
]
513 fu_issued
= fu_bitdict
[funame
]
515 # get (or set up) a latched copy of read register number
516 # and (sigh) also the read-ok flag
517 # TODO: use nmutil latchregister
518 rhname
= "%s_%s_%d" % (regfile
, regname
, i
)
519 rdflag
= Signal(name
="rdflag_%s_%s" % (funame
, rhname
),
521 if rhname
not in fu
.rf_latches
:
522 rfl
= Signal(name
="rdflag_latch_"+rhname
)
523 fu
.rf_latches
[rhname
] = rfl
524 with m
.If(fu
.issue_i
):
525 sync
+= rfl
.eq(rdflags
[i
])
527 rfl
= fu
.rf_latches
[rhname
]
529 # now the register port
530 rname
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, pi
)
531 read
= Signal
.like(_read
, name
="read_"+rname
)
532 if rname
not in fu
.rd_latches
:
533 rdl
= Signal
.like(_read
, name
="rdlatch_"+rname
)
534 fu
.rd_latches
[rname
] = rdl
535 with m
.If(fu
.issue_i
):
536 sync
+= rdl
.eq(_read
)
538 rdl
= fu
.rd_latches
[rname
]
540 # make the read immediately available on issue cycle
541 # after the read cycle, otherwies use the latched copy.
542 # this captures the regport and okflag on issue
543 with m
.If(fu
.issue_i
):
544 comb
+= read
.eq(_read
)
545 comb
+= rdflag
.eq(rdflags
[i
])
548 comb
+= rdflag
.eq(rfl
)
550 # connect request-read to picker input, and output to go-rd
551 addr_en
= Signal
.like(read
, name
="addr_en_"+name
)
552 pick
= Signal(name
="pick_"+name
) # picker input
553 rp
= Signal(name
="rp_"+name
) # picker output
554 delay_pick
= Signal(name
="dp_"+name
) # read-enable "underway"
555 rhazard
= Signal(name
="rhaz_"+name
)
557 # exclude any currently-enabled read-request (mask out active)
558 # entirely block anything hazarded from being picked
559 comb
+= pick
.eq(fu
.rd_rel_o
[idx
] & fu_active
& rdflag
&
560 ~delay_pick
& ~rhazard
)
561 comb
+= rdpick
.i
[pi
].eq(pick
)
562 comb
+= fu
.go_rd_i
[idx
].eq(delay_pick
) # pass in *delayed* pick
564 # if picked, select read-port "reg select" number to port
565 comb
+= rp
.eq(rdpick
.o
[pi
] & rdpick
.en_o
)
566 sync
+= delay_pick
.eq(rp
) # delayed "pick"
567 comb
+= addr_en
.eq(Mux(rp
, read
, 0))
569 # the read-enable happens combinatorially (see mux-bus below)
570 # but it results in the data coming out on a one-cycle delay.
574 addrs
.append(addr_en
)
577 # use the *delayed* pick signal to put requested data onto bus
578 with m
.If(delay_pick
):
579 # connect regfile port to input, creating fan-out Bus
581 print("reg connect widths",
582 regfile
, regname
, pi
, funame
,
583 src
.shape(), rport
.o_data
.shape())
584 # all FUs connect to same port
585 comb
+= src
.eq(rport
.o_data
)
587 if not self
.make_hazard_vecs
:
590 # read the write-hazard bitvector (wv) for any bit that is
591 wvchk_en
= Signal(len(wvchk
), name
="wv_chk_addr_en_"+name
)
592 issue_active
= Signal(name
="rd_iactive_"+name
)
593 # XXX combinatorial loop here
594 comb
+= issue_active
.eq(fu_active
& rdflag
)
595 with m
.If(issue_active
):
597 comb
+= wvchk_en
.eq(read
)
599 comb
+= wvchk_en
.eq(1<<read
)
600 # if FU is busy (which doesn't get set at the same time as
601 # issue) and no hazard was detected, clear wvchk_en (i.e.
602 # stop checking for hazards). there is a loop here, but it's
603 # via a DFF, so is ok. some linters may complain, but hey.
604 with m
.If(fu
.busy_o
& ~rhazard
):
605 comb
+= wvchk_en
.eq(0)
607 # read-hazard is ANDed with (filtered by) what is actually
609 comb
+= rhazard
.eq((wvchk
& wvchk_en
).bool())
611 wvens
.append(wvchk_en
)
613 # or-reduce the muxed read signals
615 # for unary-addressed
616 comb
+= rport
.ren
.eq(ortreereduce_sig(rens
))
618 # for binary-addressed
619 comb
+= rport
.addr
.eq(ortreereduce_sig(addrs
))
620 comb
+= rport
.ren
.eq(Cat(*rens
).bool())
621 print ("binary", regfile
, rpidx
, rport
, rport
.ren
, rens
, addrs
)
623 if not self
.make_hazard_vecs
:
624 return Const(0) # declare "no hazards"
626 # enable the read bitvectors for this issued instruction
627 # and return whether any write-hazard bit is set
628 wvchk_and
= Signal(len(wvchk
), name
="wv_chk_"+name
)
629 comb
+= wvchk_and
.eq(wvchk
& ortreereduce_sig(wvens
))
630 comb
+= hazard_detected
.eq(wvchk_and
.bool())
631 return hazard_detected
633 def connect_rdports(self
, m
, fu_bitdict
, fu_selected
):
634 """connect read ports
636 orders the read regspecs into a dict-of-dicts, by regfile, by
637 regport name, then connects all FUs that want that regport by
638 way of a PriorityPicker.
640 comb
, sync
= m
.d
.comb
, m
.d
.sync
645 # dictionary of lists of regfile read ports
646 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
648 # okaay, now we need a PriorityPicker per regfile per regfile port
649 # loootta pickers... peter piper picked a pack of pickled peppers...
651 for regfile
, spec
in byregfiles_rd
.items():
652 fuspecs
= byregfiles_rdspec
[regfile
]
653 rdpickers
[regfile
] = {}
655 # argh. an experiment to merge RA and RB in the INT regfile
656 # (we have too many read/write ports)
657 if self
.regreduce_en
:
659 fuspecs
['rabc'] = [fuspecs
.pop('rb')]
660 fuspecs
['rabc'].append(fuspecs
.pop('rc'))
661 fuspecs
['rabc'].append(fuspecs
.pop('ra'))
662 if regfile
== 'FAST':
663 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
664 if 'fast2' in fuspecs
:
665 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
666 if 'fast3' in fuspecs
:
667 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
669 # for each named regfile port, connect up all FUs to that port
670 # also return (and collate) hazard detection)
671 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
672 print("connect rd", regname
, fspec
)
673 rh
= self
.connect_rdport(m
, fu_bitdict
, fu_selected
,
678 return Cat(*rd_hazard
).bool()
680 def make_hazards(self
, m
, regfile
, rfile
, wvclr
, wvset
,
681 funame
, regname
, idx
,
682 addr_en
, wp
, fu
, fu_active
, wrflag
, write
,
684 """make_hazards: a setter and a clearer for the regfile write ports
686 setter is at issue time (using PowerDecoder2 regfile write numbers)
687 clearer is at regfile write time (when FU has said what to write to)
689 there is *one* unusual case here which has to be dealt with:
690 when the Function Unit does *NOT* request a write to the regfile
691 (has its data.ok bit CLEARED). this is perfectly legitimate.
694 comb
, sync
= m
.d
.comb
, m
.d
.sync
695 name
= "%s_%s_%d" % (funame
, regname
, idx
)
697 # connect up the bitvector write hazard. unlike the
698 # regfile writeports, a ONE must be written to the corresponding
699 # bit of the hazard bitvector (to indicate the existence of
702 # the detection of what shall be written to is based
703 # on *issue*. it is delayed by 1 cycle so that instructions
704 # "addi 5,5,0x2" do not cause combinatorial loops due to
705 # fake-dependency on *themselves*. this will totally fail
706 # spectacularly when doing multi-issue
707 print ("write vector (for regread)", regfile
, wvset
)
708 wviaddr_en
= Signal(len(wvset
), name
="wv_issue_addr_en_"+name
)
709 issue_active
= Signal(name
="iactive_"+name
)
710 sync
+= issue_active
.eq(fu
.issue_i
& fu_active
& wrflag
)
711 with m
.If(issue_active
):
713 comb
+= wviaddr_en
.eq(write
)
715 comb
+= wviaddr_en
.eq(1<<write
)
717 # deal with write vector clear: this kicks in when the regfile
718 # is written to, and clears the corresponding bitvector entry
719 print ("write vector", regfile
, wvclr
)
720 wvaddr_en
= Signal(len(wvclr
), name
="wvaddr_en_"+name
)
722 comb
+= wvaddr_en
.eq(addr_en
)
725 comb
+= wvaddr_en
.eq(1<<addr_en
)
727 # XXX ASSUME that LDSTFunctionUnit always sets the data it intends to
728 # this may NOT be the case when an exception occurs
729 if isinstance(fu
, LDSTFunctionUnit
):
730 return wvaddr_en
, wviaddr_en
732 # okaaay, this is preparation for the awkward case.
733 # * latch a copy of wrflag when issue goes high.
734 # * when the fu_wrok (data.ok) flag is NOT set,
735 # but the FU is done, the FU is NEVER going to write
736 # so the bitvector has to be cleared.
737 latch_wrflag
= Signal(name
="latch_wrflag_"+name
)
738 with m
.If(~fu
.busy_o
):
739 sync
+= latch_wrflag
.eq(0)
740 with m
.If(fu
.issue_i
& fu_active
):
741 sync
+= latch_wrflag
.eq(wrflag
)
742 with m
.If(fu
.alu_done_o
& latch_wrflag
& ~fu_wrok
):
744 comb
+= wvaddr_en
.eq(write
) # addr_en gated with wp, don't use
746 comb
+= wvaddr_en
.eq(1<<addr_en
) # binary addr_en not gated
748 return wvaddr_en
, wviaddr_en
750 def connect_wrport(self
, m
, fu_bitdict
, fu_selected
,
751 wrpickers
, regfile
, regname
, fspec
):
752 comb
, sync
= m
.d
.comb
, m
.d
.sync
758 # select the required write port. these are pre-defined sizes
759 rfile
= regs
.rf
[regfile
.lower()]
760 wport
= rfile
.w_ports
[rpidx
]
762 print("connect wr", regname
, "unary", rfile
.unary
, fspec
)
763 print(regfile
, regs
.rf
.keys())
765 # select the write-protection hazard vector. note that this still
766 # requires to WRITE to the hazard bitvector! read-requests need
767 # to RAISE the bitvector (set it to 1), which, duh, requires a WRITE
768 if self
.make_hazard_vecs
:
769 wv
= regs
.wv
[regfile
.lower()]
770 wvset
= wv
.s
# write-vec bit-level hazard ctrl
771 wvclr
= wv
.r
# write-vec bit-level hazard ctrl
772 wvchk
= wv
.q
# write-after-write hazard check
773 wvchk_qint
= wv
.q
# write-after-write hazard check, NOT delayed
776 if not isinstance(fspecs
, list):
783 for i
, fspec
in enumerate(fspecs
):
784 # get the regfile specs for this regfile port
785 (wf
, _write
, wid
, fuspecs
) = \
786 (fspec
.okflag
, fspec
.regport
, fspec
.wid
, fspec
.specs
)
787 print ("fpsec", i
, "wrflag", wf
, fspec
, len(fuspecs
))
788 ppoffs
.append(pplen
) # record offset for picker
789 pplen
+= len(fuspecs
)
791 name
= "%s_%s_%d" % (regfile
, regname
, i
)
792 wrflag
= Signal(name
="wr_flag_"+name
)
794 comb
+= wrflag
.eq(wf
)
797 wrflags
.append(wrflag
)
799 # create a priority picker to manage this port
800 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(pplen
)
801 m
.submodules
["wrpick_%s_%s" % (regfile
, rpidx
)] = wrpick
808 #wvens = [] - not needed: reading of writevec is permanently held hi
810 for i
, fspec
in enumerate(fspecs
):
811 # connect up the FU req/go signals and the reg-read to the FU
812 # these are arbitrated by Data.ok signals
813 (wf
, _write
, wid
, fuspecs
) = \
814 (fspec
.okflag
, fspec
.regport
, fspec
.wid
, fspec
.specs
)
815 for pi
, fuspec
in enumerate(fspec
.specs
):
816 (funame
, fu
, idx
) = (fuspec
.funame
, fuspec
.fu
, fuspec
.idx
)
817 fu_requested
= fu_bitdict
[funame
]
819 name
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, idx
)
820 # get (or set up) a write-latched copy of write register number
821 write
= Signal
.like(_write
, name
="write_"+name
)
822 rname
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, idx
)
823 if rname
not in fu
.wr_latches
:
824 wrl
= Signal
.like(_write
, name
="wrlatch_"+rname
)
825 fu
.wr_latches
[rname
] = write
826 # do not depend on fu.issue_i here, it creates a
827 # combinatorial loop on waw checking. using the FU
828 # "enable" bitdict entry for this FU is sufficient,
829 # because the PowerDecoder2 read/write nums are
830 # valid continuously when the instruction is valid
831 with m
.If(fu_requested
):
832 sync
+= wrl
.eq(_write
)
833 comb
+= write
.eq(_write
)
835 comb
+= write
.eq(wrl
)
837 write
= fu
.wr_latches
[rname
]
839 # write-request comes from dest.ok
840 dest
= fu
.get_out(idx
)
841 fu_dest_latch
= fu
.get_fu_out(idx
) # latched output
842 name
= "%s_%s_%d" % (funame
, regname
, idx
)
843 fu_wrok
= Signal(name
="fu_wrok_"+name
, reset_less
=True)
844 comb
+= fu_wrok
.eq(dest
.ok
& fu
.busy_o
)
846 # connect request-write to picker input, and output to go-wr
847 fu_active
= fu_selected
[funame
]
848 pick
= fu
.wr
.rel_o
[idx
] & fu_active
849 comb
+= wrpick
.i
[pi
].eq(pick
)
850 # create a single-pulse go write from the picker output
851 wr_pick
= Signal(name
="wpick_%s_%s_%d" % (funame
, regname
, idx
))
852 comb
+= wr_pick
.eq(wrpick
.o
[pi
] & wrpick
.en_o
)
853 comb
+= fu
.go_wr_i
[idx
].eq(rising_edge(m
, wr_pick
))
855 # connect the regspec write "reg select" number to this port
856 # only if one FU actually requests (and is granted) the port
857 # will the write-enable be activated
858 wname
= "waddr_en_%s_%s_%d" % (funame
, regname
, idx
)
859 addr_en
= Signal
.like(write
, name
=wname
)
861 comb
+= wp
.eq(wr_pick
& wrpick
.en_o
)
862 comb
+= addr_en
.eq(Mux(wp
, write
, 0))
866 addrs
.append(addr_en
)
869 # connect regfile port to input
870 print("reg connect widths",
871 regfile
, regname
, pi
, funame
,
872 dest
.shape(), wport
.i_data
.shape())
873 wsigs
.append(fu_dest_latch
)
875 # now connect up the bitvector write hazard
876 if not self
.make_hazard_vecs
:
878 res
= self
.make_hazards(m
, regfile
, rfile
, wvclr
, wvset
,
879 funame
, regname
, idx
,
880 addr_en
, wp
, fu
, fu_active
,
881 wrflags
[i
], write
, fu_wrok
)
882 wvaddr_en
, wv_issue_en
= res
883 wvclren
.append(wvaddr_en
) # set only: no data => clear bit
884 wvseten
.append(wv_issue_en
) # set data same as enable
886 # read the write-hazard bitvector (wv) for any bit that is
887 fu_requested
= fu_bitdict
[funame
]
888 wvchk_en
= Signal(len(wvchk
), name
="waw_chk_addr_en_"+name
)
889 issue_active
= Signal(name
="waw_iactive_"+name
)
890 whazard
= Signal(name
="whaz_"+name
)
892 # XXX EEK! STATE regfile (branch) does not have an
893 # write-active indicator in regspec_decode_write()
894 print ("XXX FIXME waw_iactive", issue_active
,
897 # check bits from the incoming instruction. note (back
898 # in connect_instruction) that the decoder is held for
899 # us to be able to do this, here... *without* issue being
900 # held HI. we MUST NOT gate this with fu.issue_i or
901 # with fu_bitdict "enable": it would create a loop
902 comb
+= issue_active
.eq(wf
)
903 with m
.If(issue_active
):
905 comb
+= wvchk_en
.eq(write
)
907 comb
+= wvchk_en
.eq(1<<write
)
908 # if FU is busy (which doesn't get set at the same time as
909 # issue) and no hazard was detected, clear wvchk_en (i.e.
910 # stop checking for hazards). there is a loop here, but it's
911 # via a DFF, so is ok. some linters may complain, but hey.
912 with m
.If(fu
.busy_o
& ~whazard
):
913 comb
+= wvchk_en
.eq(0)
915 # write-hazard is ANDed with (filtered by) what is actually
916 # being requested. the wvchk data is on a one-clock delay,
917 # and wvchk_en comes directly from the main decoder
918 comb
+= whazard
.eq((wvchk_qint
& wvchk_en
).bool())
920 comb
+= fu
._waw
_hazard
.eq(1)
922 #wvens.append(wvchk_en)
924 # here is where we create the Write Broadcast Bus. simple, eh?
925 comb
+= wport
.i_data
.eq(ortreereduce_sig(wsigs
))
927 # for unary-addressed
928 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
930 # for binary-addressed
931 comb
+= wport
.addr
.eq(ortreereduce_sig(addrs
))
932 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
934 if not self
.make_hazard_vecs
:
937 # return these here rather than set wvclr/wvset directly,
938 # because there may be more than one write-port to a given
939 # regfile. example: XER has a write-port for SO, CA, and OV
940 # and the *last one added* of those would overwrite the other
941 # two. solution: have connect_wrports collate all the
942 # or-tree-reduced bitvector set/clear requests and drop them
943 # in as a single "thing". this can only be done because the
944 # set/get is an unary bitvector.
945 print ("make write-vecs", regfile
, regname
, wvset
, wvclr
)
946 return (wvclren
, # clear (regfile write)
947 wvseten
) # set (issue time)
949 def connect_wrports(self
, m
, fu_bitdict
, fu_selected
):
950 """connect write ports
952 orders the write regspecs into a dict-of-dicts, by regfile,
953 by regport name, then connects all FUs that want that regport
954 by way of a PriorityPicker.
956 note that the write-port wen, write-port data, and go_wr_i all need to
957 be on the exact same clock cycle. as there is a combinatorial loop bug
958 at the moment, these all use sync.
960 comb
, sync
= m
.d
.comb
, m
.d
.sync
963 # dictionary of lists of regfile write ports
964 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
966 # same for write ports.
967 # BLECH! complex code-duplication! BLECH!
969 wvclrers
= defaultdict(list)
970 wvseters
= defaultdict(list)
971 for regfile
, spec
in byregfiles_wr
.items():
972 fuspecs
= byregfiles_wrspec
[regfile
]
973 wrpickers
[regfile
] = {}
975 if self
.regreduce_en
:
976 # argh, more port-merging
978 fuspecs
['o'] = [fuspecs
.pop('o')]
979 fuspecs
['o'].append(fuspecs
.pop('o1'))
980 if regfile
== 'FAST':
981 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
982 if 'fast2' in fuspecs
:
983 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
984 if 'fast3' in fuspecs
:
985 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
987 # collate these and record them by regfile because there
988 # are sometimes more write-ports per regfile
989 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
990 wvclren
, wvseten
= self
.connect_wrport(m
,
991 fu_bitdict
, fu_selected
,
993 regfile
, regname
, fspec
)
994 wvclrers
[regfile
.lower()].append(wvclren
)
995 wvseters
[regfile
.lower()].append(wvseten
)
997 if not self
.make_hazard_vecs
:
1000 # for write-vectors: reduce the clr-ers and set-ers down to
1001 # a single set of bits. otherwise if there are two write
1002 # ports (on some regfiles), the last one doing comb += on
1003 # the reg.wv[regfile] instance "wins" (and all others are ignored,
1004 # whoops). if there was only one write-port per wv regfile this would
1006 for regfile
in wvclrers
.keys():
1007 wv
= regs
.wv
[regfile
]
1008 wvset
= wv
.s
# write-vec bit-level hazard ctrl
1009 wvclr
= wv
.r
# write-vec bit-level hazard ctrl
1010 wvclren
= wvclrers
[regfile
]
1011 wvseten
= wvseters
[regfile
]
1012 comb
+= wvclr
.eq(ortreereduce_sig(wvclren
)) # clear (regfile write)
1013 comb
+= wvset
.eq(ortreereduce_sig(wvseten
)) # set (issue time)
1015 def get_byregfiles(self
, readmode
):
1017 mode
= "read" if readmode
else "write"
1020 e
= self
.ireg
.e
# decoded instruction to execute
1022 # dictionary of dictionaries of lists/tuples of regfile ports.
1023 # first key: regfile. second key: regfile port name
1024 byregfiles
= defaultdict(lambda: defaultdict(list))
1025 byregfiles_spec
= defaultdict(dict)
1027 for (funame
, fu
) in fus
.items():
1028 # create in each FU a receptacle for the read/write register
1029 # hazard numbers. to be latched in connect_rd/write_ports
1030 # XXX better that this is moved into the actual FUs, but
1031 # the issue there is that this function is actually better
1032 # suited at the moment
1034 fu
.rd_latches
= {} # read reg number latches
1035 fu
.rf_latches
= {} # read flag latches
1039 print("%s ports for %s" % (mode
, funame
))
1040 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
1041 # construct regfile specs: read uses inspec, write outspec
1042 (regfile
, regname
, wid
) = fu
.get_io_spec(readmode
, idx
)
1043 print(" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
1045 # the PowerDecoder2 (main one, not the satellites) contains
1046 # the decoded regfile numbers. obtain these now
1047 okflag
, regport
= regspec_decode(readmode
, e
, regfile
, regname
)
1049 # construct the dictionary of regspec information by regfile
1050 if regname
not in byregfiles_spec
[regfile
]:
1051 byregfiles_spec
[regfile
][regname
] = \
1052 ByRegSpec(okflag
, regport
, wid
, [])
1053 # here we start to create "lanes"
1054 fuspec
= FUSpec(funame
, fu
, idx
)
1055 byregfiles
[regfile
][idx
].append(fuspec
)
1056 byregfiles_spec
[regfile
][regname
].specs
.append(fuspec
)
1058 # ok just print that all out, for convenience
1059 for regfile
, spec
in byregfiles
.items():
1060 print("regfile %s ports:" % mode
, regfile
)
1061 fuspecs
= byregfiles_spec
[regfile
]
1062 for regname
, fspec
in fuspecs
.items():
1063 [okflag
, regport
, wid
, fuspecs
] = fspec
1064 print(" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
1065 print(" %s" % regname
, wid
, okflag
, regport
)
1066 for (funame
, fu
, idx
) in fuspecs
:
1067 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
1068 print(" ", funame
, fu
.__class
__.__name
__, idx
, fusig
)
1071 return byregfiles
, byregfiles_spec
1074 yield from self
.fus
.ports()
1075 yield from self
.i
.e
.ports()
1076 yield from self
.l0
.ports()
1083 if __name__
== '__main__':
1084 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
1090 dut
= NonProductionCore(pspec
)
1091 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
1092 with
open("test_core.il", "w") as f
: