src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from FastRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import Elaboratable, Module, Signal
  19 from nmigen.cli import rtlil
  20
  21
  22 from soc.decoder.decode2execute1 import Data
  23 from soc.experiment.testmem import TestMemory # test only for instructions
  24 from soc.regfile.regfiles import FastRegs
  25 from soc.simple.core import NonProductionCore
  26
  27
  28 class TestIssuer(Elaboratable):
  29     """TestIssuer - reads instructions from TestMemory and issues them
  30
  31     efficiency and speed is not the main goal here: functional correctness is.
  32     """
  33     def __init__(self, addrwid=6, idepth=6):
  34         # main instruction core
  35         self.core = core = NonProductionCore(addrwid)
  36
  37         # Test Instruction memory
  38         self.imem = TestMemory(32, idepth)
  39         self.i_rd = self.imem.rdport
  40         #self.i_wr = self.imem.write_port() errr...
  41
  42         # instruction go/monitor
  43         self.go_insn_i = Signal(reset_less=True)
  44         self.pc_o = Signal(64, reset_less=True)
  45         self.pc_i = Data(64, "pc") # set "ok" to indicate "please change me"
  46         self.busy_o = core.busy_o
  47         self.memerr_o = Signal(reset_less=True)
  48
  49         # FAST regfile read /write ports
  50         self.fast_rd1 = self.core.regs.rf['fast'].r_ports['d_rd1']
  51         self.fast_wr1 = self.core.regs.rf['fast'].w_ports['d_wr1']
  52         # hack method of keeping an eye on whether branch/trap set the PC
  53         self.fast_nia = self.core.regs.rf['fast'].w_ports['nia']
  54         self.fast_nia.wen.name = 'fast_nia_wen'
  55
  56     def elaborate(self, platform):
  57         m = Module()
  58         comb, sync = m.d.comb, m.d.sync
  59
  60         m.submodules.core = core = self.core
  61         m.submodules.imem = imem = self.imem
  62
  63         # temporary hack: says "go" immediately for both address gen and ST
  64         l0 = core.l0
  65         ldst = core.fus.fus['ldst0']
  66         m.d.comb += ldst.ad.go.eq(ldst.ad.rel) # link addr-go direct to rel
  67         m.d.comb += ldst.st.go.eq(ldst.st.rel) # link store-go direct to rel
  68
  69         # PC and instruction from I-Memory
  70         current_insn = Signal(32) # current fetched instruction (note sync)
  71         current_pc = Signal(64) # current PC (note it is reset/sync)
  72         pc_changed = Signal() # note write to PC
  73         comb += self.pc_o.eq(current_pc)
  74         ilatch = Signal(32)
  75
  76         # next instruction (+4 on current)
  77         nia = Signal(64, reset_less=True)
  78         comb += nia.eq(current_pc + 4)
  79
  80         # temporaries
  81         core_busy_o = core.busy_o         # core is busy
  82         core_ivalid_i = core.ivalid_i     # instruction is valid
  83         core_issue_i = core.issue_i       # instruction is issued
  84         core_be_i = core.bigendian_i      # bigendian mode
  85         core_opcode_i = core.raw_opcode_i # raw opcode
  86
  87         # actually use a nmigen FSM for the first time (w00t)
  88         with m.FSM() as fsm:
  89
  90             # waiting (zzz)
  91             with m.State("IDLE"):
  92                 sync += pc_changed.eq(0)
  93                 with m.If(self.go_insn_i):
  94                     # instruction allowed to go: start by reading the PC
  95                     pc = Signal(64, reset_less=True)
  96                     with m.If(self.pc_i.ok):
  97                         # incoming override (start from pc_i)
  98                         comb += pc.eq(self.pc_i.data)
  99                     with m.Else():
 100                         # otherwise read FastRegs regfile for PC
 101                         comb += self.fast_rd1.ren.eq(1<<FastRegs.PC)
 102                         comb += pc.eq(self.fast_rd1.data_o)
 103                     # capture the PC and also drop it into Insn Memory
 104                     # we have joined a pair of combinatorial memory
 105                     # lookups together.  this is Generally Bad.
 106                     comb += self.i_rd.addr.eq(pc[2:]) # ignore last 2 bits
 107                     comb += current_insn.eq(self.i_rd.data)
 108                     sync += current_pc.eq(pc)
 109                     m.next = "INSN_READ" # move to "issue" phase
 110
 111             # got the instruction: start issue
 112             with m.State("INSN_READ"):
 113                 comb += current_insn.eq(self.i_rd.data)
 114                 comb += core_ivalid_i.eq(1) # say instruction is valid
 115                 comb += core_issue_i.eq(1)  # and issued (ivalid_i redundant)
 116                 comb += core_be_i.eq(0)     # little-endian mode
 117                 comb += core_opcode_i.eq(current_insn) # actual opcode
 118                 sync += ilatch.eq(current_insn)
 119                 m.next = "INSN_ACTIVE" # move to "wait for completion" phase
 120
 121             # instruction started: must wait till it finishes
 122             with m.State("INSN_ACTIVE"):
 123                 comb += core_ivalid_i.eq(1) # say instruction is valid
 124                 comb += core_opcode_i.eq(ilatch) # actual opcode
 125                 #sync += core_issue_i.eq(0) # issue raises for only one cycle
 126                 with m.If(self.fast_nia.wen):
 127                     sync += pc_changed.eq(1)
 128                 with m.If(~core_busy_o): # instruction done!
 129                     #sync += core_ivalid_i.eq(0) # say instruction is invalid
 130                     #sync += core_opcode_i.eq(0) # clear out (no good reason)
 131                     # ok here we are not reading the branch unit.  TODO
 132                     # this just blithely overwrites whatever pipeline updated
 133                     # the PC
 134                     with m.If(~pc_changed):
 135                         comb += self.fast_wr1.wen.eq(1<<FastRegs.PC)
 136                         comb += self.fast_wr1.data_i.eq(nia)
 137                     m.next = "IDLE" # back to idle
 138
 139         return m
 140
 141     def __iter__(self):
 142         yield from self.pc_i.ports()
 143         yield self.pc_o
 144         yield self.go_insn_i
 145         yield self.memerr_o
 146         yield from self.core.ports()
 147         yield from self.imem.ports()
 148
 149     def ports(self):
 150         return list(self)
 151
 152
 153 if __name__ == '__main__':
 154     dut = TestIssuer()
 155     vl = rtlil.convert(dut, ports=dut.ports())
 156     with open("test_issuer.il", "w") as f:
 157         f.write(vl)
 158