1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.power_decoder
import create_pdecode
7 from soc
.decoder
.power_decoder2
import PowerDecode2
8 from soc
.decoder
.isa
.all
import ISA
9 from soc
.decoder
.power_enums
import Function
12 from soc
.simple
.core
import NonProductionCore
13 from soc
.experiment
.compalu_multi
import find_ok
# hack
15 # test with ALU data and Logical data
16 from soc
.fu
.alu
.test
.test_pipe_caller
import TestCase
, ALUTestCase
, test_data
17 #from soc.fu.logical.test.test_pipe_caller import LogicalTestCase, test_data
20 def set_cu_input(cu
, idx
, data
):
21 rdop
= cu
.get_in_name(idx
)
22 yield cu
.src_i
[idx
].eq(data
)
24 rd_rel_o
= yield cu
.rd
.rel
[idx
]
25 print ("rd_rel %d wait HI" % idx
, rd_rel_o
, rdop
, hex(data
))
29 yield cu
.rd
.go
[idx
].eq(1)
32 rd_rel_o
= yield cu
.rd
.rel
[idx
]
35 print ("rd_rel %d wait HI" % idx
, rd_rel_o
)
37 yield cu
.rd
.go
[idx
].eq(0)
38 yield cu
.src_i
[idx
].eq(0)
41 def get_cu_output(cu
, idx
, code
):
42 wrmask
= yield cu
.wrmask
43 wrop
= cu
.get_out_name(idx
)
44 wrok
= cu
.get_out(idx
)
45 fname
= find_ok(wrok
.fields
)
46 wrok
= yield getattr(wrok
, fname
)
47 print ("wr_rel mask", repr(code
), idx
, wrop
, bin(wrmask
), fname
, wrok
)
48 assert wrmask
& (1<<idx
), \
49 "get_cu_output '%s': mask bit %d not set\n" \
50 "write-operand '%s' Data.ok likely not set (%s)" \
51 % (code
, idx
, wrop
, hex(wrok
))
53 wr_relall_o
= yield cu
.wr
.rel
54 wr_rel_o
= yield cu
.wr
.rel
[idx
]
55 print ("wr_rel %d wait" % idx
, hex(wr_relall_o
), wr_rel_o
)
59 yield cu
.wr
.go
[idx
].eq(1)
61 result
= yield cu
.dest
[idx
]
63 yield cu
.wr
.go
[idx
].eq(0)
64 print ("result", repr(code
), idx
, wrop
, wrok
, hex(result
))
68 def set_cu_inputs(cu
, inp
):
69 for idx
, data
in inp
.items():
70 yield from set_cu_input(cu
, idx
, data
)
73 def set_issue(core
, dec2
, sim
):
74 yield core
.issue_i
.eq(1)
76 yield core
.issue_i
.eq(0)
78 busy_o
= yield core
.busy_o
85 def wait_for_busy_clear(cu
):
87 busy_o
= yield cu
.busy_o
94 def get_cu_outputs(cu
, code
):
96 for i
in range(cu
.n_dst
):
97 wr_rel_o
= yield cu
.wr
.rel
[i
]
99 result
= yield from get_cu_output(cu
, i
, code
)
100 wrop
= cu
.get_out_name(i
)
101 print ("output", i
, wrop
, hex(result
))
106 def get_inp_indexed(cu
, inp
):
108 for i
in range(cu
.n_src
):
109 wrop
= cu
.get_in_name(i
)
115 class TestRunner(FHDLTestCase
):
116 def __init__(self
, tst_data
):
117 super().__init
__("run_all")
118 self
.test_data
= tst_data
123 instruction
= Signal(32)
126 m
.submodules
.core
= core
= NonProductionCore()
127 pdecode
= core
.pdecode
128 pdecode2
= core
.pdecode2
130 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
131 comb
+= core
.ivalid_i
.eq(ivalid_i
)
137 yield core
.issue_i
.eq(0)
140 for test
in self
.test_data
:
142 program
= test
.program
143 self
.subTest(test
.name
)
144 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, 0)
145 gen
= program
.generate_instructions()
146 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
148 # set up INT regfile, "direct" write from sim data
150 yield core
.regs
.int.regs
[i
].reg
.eq(test
.regs
[i
])
152 index
= sim
.pc
.CIA
.value
//4
153 while index
< len(instructions
):
154 ins
, code
= instructions
[index
]
156 print("0x{:X}".format(ins
& 0xffffffff))
159 # ask the decoder to decode this binary data (endian'd)
160 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
161 yield instruction
.eq(ins
) # raw binary instr.
164 #fn_unit = yield pdecode2.e.fn_unit
165 #fuval = self.funit.value
166 #self.assertEqual(fn_unit & fuval, fuval)
168 # set operand and get inputs
169 yield from set_issue(core
, pdecode2
, sim
)
172 yield from wait_for_busy_clear(core
)
177 # call simulated operation
178 opname
= code
.split(' ')[0]
179 yield from sim
.call(opname
)
180 index
= sim
.pc
.CIA
.value
//4
185 rval
= yield core
.regs
.int.regs
[i
].reg
187 print ("int regs", list(map(hex, intregs
)))
189 simregval
= sim
.gpr
[i
].asint()
190 self
.assertEqual(simregval
, intregs
[i
],
191 "int reg %d not equal %s" % (i
, repr(code
)))
193 sim
.add_sync_process(process
)
194 with sim
.write_vcd("core_simulator.vcd", "core_simulator.gtkw",
199 if __name__
== "__main__":
200 unittest
.main(exit
=False)
201 suite
= unittest
.TestSuite()
202 suite
.addTest(TestRunner(test_data
))
204 runner
= unittest
.TextTestRunner()