src/soc/simple/test/test_issuer.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.isa.all import ISA
  14 from soc.decoder.power_enums import Function, XER_bits
  15 from soc.config.endian import bigendian
  16
  17 from soc.simple.issuer import TestIssuer
  18 from soc.experiment.compalu_multi import find_ok  # hack
  19
  20 from soc.config.test.test_loadstore import TestMemPspec
  21 from soc.simple.test.test_core import (setup_regs, check_regs,
  22                                        wait_for_busy_clear,
  23                                        wait_for_busy_hi)
  24 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  25                                                  check_sim_memory)
  26
  27 # test with ALU data and Logical data
  28 #from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  29 #from soc.fu.div.test.test_pipe_caller import DivTestCase
  30 #from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  31 #from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  32 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  33 #from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  34 #from soc.fu.spr.test.test_pipe_caller import SPRTestCase
  35 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  36 from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
  37 #from soc.simulator.test_helloworld_sim import HelloTestCases
  38
  39
  40 def setup_i_memory(imem, startaddr, instructions):
  41     mem = imem
  42     print("insn before, init mem", mem.depth, mem.width, mem,
  43           len(instructions))
  44     for i in range(mem.depth):
  45         yield mem._array[i].eq(0)
  46     yield Settle()
  47     startaddr //= 4 # instructions are 32-bit
  48     if mem.width == 32:
  49         mask = ((1<<32)-1)
  50         for ins in instructions:
  51             if isinstance(ins, tuple):
  52                 insn, code = ins
  53             else:
  54                 insn, code = ins, ''
  55             insn = insn & 0xffffffff
  56             yield mem._array[startaddr].eq(insn)
  57             yield Settle()
  58             if insn != 0:
  59                 print ("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  60             startaddr += 1
  61             startaddr = startaddr & mask
  62         return
  63
  64     # 64 bit
  65     mask = ((1<<64)-1)
  66     for ins in instructions:
  67         if isinstance(ins, tuple):
  68             insn, code = ins
  69         else:
  70             insn, code = ins, ''
  71         insn = insn & 0xffffffff
  72         msbs = (startaddr >> 1) & mask
  73         val = yield mem._array[msbs]
  74         if insn != 0:
  75             print("before set", hex(4*startaddr),
  76                   hex(msbs), hex(val), hex(insn))
  77         lsb = 1 if (startaddr & 1) else 0
  78         val = (val | (insn << (lsb*32)))
  79         val = val & mask
  80         yield mem._array[msbs].eq(val)
  81         yield Settle()
  82         if insn != 0:
  83             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  84             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  85         startaddr += 1
  86         startaddr = startaddr & mask
  87
  88
  89 class TestRunner(FHDLTestCase):
  90     def __init__(self, tst_data):
  91         super().__init__("run_all")
  92         self.test_data = tst_data
  93
  94     def run_all(self):
  95         m = Module()
  96         comb = m.d.comb
  97         go_insn_i = Signal()
  98         pc_i = Signal(32)
  99
 100         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
 101                              imem_ifacetype='test_bare_wb',
 102                              addr_wid=48,
 103                              mask_wid=8,
 104                              imem_reg_wid=64,
 105                              reg_wid=64)
 106         m.submodules.issuer = issuer = TestIssuer(pspec)
 107         imem = issuer.imem._get_memory()
 108         core = issuer.core
 109         pdecode2 = core.pdecode2
 110         l0 = core.l0
 111
 112         comb += issuer.pc_i.data.eq(pc_i)
 113         comb += issuer.go_insn_i.eq(go_insn_i)
 114
 115         # nmigen Simulation
 116         sim = Simulator(m)
 117         sim.add_clock(1e-6)
 118
 119         def process():
 120
 121             for test in self.test_data:
 122
 123                 # get core going
 124                 yield issuer.core_bigendian_i.eq(bigendian)
 125                 yield issuer.core_start_i.eq(1)
 126                 yield
 127                 yield issuer.core_start_i.eq(0)
 128                 yield Settle()
 129
 130                 print(test.name)
 131                 program = test.program
 132                 self.subTest(test.name)
 133                 print("regs", test.regs)
 134                 print("sprs", test.sprs)
 135                 print("cr", test.cr)
 136                 print("mem", test.mem)
 137                 print("msr", test.msr)
 138                 print("assem", program.assembly)
 139                 gen = list(program.generate_instructions())
 140                 insncode = program.assembly.splitlines()
 141                 instructions = list(zip(gen, insncode))
 142                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
 143                           test.msr,
 144                           initial_insns=gen, respect_pc=True,
 145                           disassembly=insncode,
 146                           bigendian=bigendian)
 147
 148                 pc = 0  # start address
 149
 150                 yield from setup_i_memory(imem, pc, instructions)
 151                 yield from setup_test_memory(l0, sim)
 152                 yield from setup_regs(core, test)
 153
 154                 yield pc_i.eq(pc)
 155                 yield issuer.pc_i.ok.eq(1)
 156
 157                 index = sim.pc.CIA.value//4
 158                 while index < len(instructions):
 159                     ins, code = instructions[index]
 160
 161                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 162                     print(index, code)
 163
 164                     # start the instruction
 165                     yield go_insn_i.eq(1)
 166                     yield
 167                     yield issuer.pc_i.ok.eq(0)  # don't change PC from now on
 168                     yield go_insn_i.eq(0)      # and don't issue a new insn
 169                     yield Settle()
 170
 171                     # wait until executed
 172                     yield from wait_for_busy_hi(core)
 173                     yield from wait_for_busy_clear(core)
 174
 175                     terminated = yield issuer.halted_o
 176                     print("terminated", terminated)
 177
 178                     print("sim", code)
 179                     # call simulated operation
 180                     opname = code.split(' ')[0]
 181                     yield from sim.call(opname)
 182                     yield Settle()
 183                     index = sim.pc.CIA.value//4
 184
 185                     # register check
 186                     yield from check_regs(self, sim, core, test, code)
 187
 188                     # Memory check
 189                     yield from check_sim_memory(self, l0, sim, code)
 190
 191                     terminated = yield issuer.halted_o
 192                     if terminated:
 193                         break
 194
 195         sim.add_sync_process(process)
 196         with sim.write_vcd("issuer_simulator.vcd",
 197                            traces=[]):
 198             sim.run()
 199
 200
 201 if __name__ == "__main__":
 202     unittest.main(exit=False)
 203     suite = unittest.TestSuite()
 204     # suite.addTest(TestRunner(HelloTestCases.test_data))
 205     # suite.addTest(TestRunner(DivTestCase.test_data))
 206     suite.addTest(TestRunner(AttnTestCase.test_data))
 207     suite.addTest(TestRunner(GeneralTestCases.test_data))
 208     suite.addTest(TestRunner(LDSTTestCase().test_data))
 209     suite.addTest(TestRunner(CRTestCase().test_data))
 210     # suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 211     # suite.addTest(TestRunner(LogicalTestCase.test_data))
 212     # suite.addTest(TestRunner(ALUTestCase.test_data))
 213     # suite.addTest(TestRunner(BranchTestCase.test_data))
 214     # suite.addTest(TestRunner(SPRTestCase.test_data))
 215
 216     runner = unittest.TextTestRunner()
 217     runner.run(suite)