1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
8 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
9 from nmutil
.formaltest
import FHDLTestCase
10 from nmigen
.cli
import rtlil
12 from soc
.decoder
.isa
.caller
import special_sprs
13 from soc
.decoder
.isa
.all
import ISA
14 from soc
.decoder
.power_enums
import Function
, XER_bits
15 from soc
.config
.endian
import bigendian
17 from soc
.simple
.issuer
import TestIssuer
18 from soc
.experiment
.compalu_multi
import find_ok
# hack
20 from soc
.config
.test
.test_loadstore
import TestMemPspec
21 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
24 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
27 # test with ALU data and Logical data
28 #from soc.fu.alu.test.test_pipe_caller import ALUTestCase
29 #from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
30 #from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
31 #from soc.fu.cr.test.test_pipe_caller import CRTestCase
32 #from soc.fu.branch.test.test_pipe_caller import BranchTestCase
33 #from soc.fu.spr.test.test_pipe_caller import SPRTestCase
34 from soc
.fu
.ldst
.test
.test_pipe_caller
import LDSTTestCase
35 from soc
.simulator
.test_sim
import (GeneralTestCases
, AttnTestCase
)
36 #from soc.simulator.test_helloworld_sim import HelloTestCases
39 def setup_i_memory(imem
, startaddr
, instructions
):
41 print ("insn before, init mem", mem
.depth
, mem
.width
, mem
,
43 for i
in range(mem
.depth
):
44 yield mem
._array
[i
].eq(0)
46 startaddr
//= 4 # instructions are 32-bit
48 for ins
in instructions
:
49 if isinstance(ins
, tuple):
53 insn
= insn
& 0xffffffff
54 msbs
= (startaddr
>>1) & mask
55 val
= yield mem
._array
[msbs
]
57 print ("before set", hex(4*startaddr
),
58 hex(msbs
), hex(val
), hex(insn
))
59 lsb
= 1 if (startaddr
& 1) else 0
60 val
= (val |
(insn
<< (lsb
*32)))
62 yield mem
._array
[msbs
].eq(val
)
65 print ("after set", hex(4*startaddr
), hex(msbs
), hex(val
))
66 print ("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
68 startaddr
= startaddr
& mask
71 class TestRunner(FHDLTestCase
):
72 def __init__(self
, tst_data
):
73 super().__init
__("run_all")
74 self
.test_data
= tst_data
82 pspec
= TestMemPspec(ldst_ifacetype
='test_bare_wb',
83 imem_ifacetype
='test_bare_wb',
87 m
.submodules
.issuer
= issuer
= TestIssuer(pspec
)
88 imem
= issuer
.imem
._get
_memory
()
90 pdecode2
= core
.pdecode2
93 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
94 comb
+= issuer
.go_insn_i
.eq(go_insn_i
)
102 for test
in self
.test_data
:
105 yield core
.bigendian_i
.eq(bigendian
)
106 yield core
.core_start_i
.eq(1)
108 yield core
.core_start_i
.eq(0)
112 program
= test
.program
113 self
.subTest(test
.name
)
114 print ("regs", test
.regs
)
115 print ("sprs", test
.sprs
)
116 print ("cr", test
.cr
)
117 print ("mem", test
.mem
)
118 print ("msr", test
.msr
)
119 print ("assem", program
.assembly
)
120 gen
= list(program
.generate_instructions())
121 insncode
= program
.assembly
.splitlines()
122 instructions
= list(zip(gen
, insncode
))
123 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
125 initial_insns
=gen
, respect_pc
=True,
126 disassembly
=insncode
,
129 pc
= 0 # start address
131 yield from setup_i_memory(imem
, pc
, instructions
)
132 yield from setup_test_memory(l0
, sim
)
133 yield from setup_regs(core
, test
)
136 yield issuer
.pc_i
.ok
.eq(1)
138 index
= sim
.pc
.CIA
.value
//4
139 while index
< len(instructions
):
140 ins
, code
= instructions
[index
]
142 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
145 # start the instruction
146 yield go_insn_i
.eq(1)
148 yield issuer
.pc_i
.ok
.eq(0) # don't change PC from now on
149 yield go_insn_i
.eq(0) # and don't issue a new insn
152 # wait until executed
153 yield from wait_for_busy_hi(core
)
154 yield from wait_for_busy_clear(core
)
156 terminated
= yield core
.core_terminated_o
157 print ("terminated", terminated
)
160 # call simulated operation
161 opname
= code
.split(' ')[0]
162 yield from sim
.call(opname
)
164 index
= sim
.pc
.CIA
.value
//4
167 yield from check_regs(self
, sim
, core
, test
, code
)
170 yield from check_sim_memory(self
, l0
, sim
, code
)
172 terminated
= yield core
.core_terminated_o
176 sim
.add_sync_process(process
)
177 with sim
.write_vcd("issuer_simulator.vcd",
182 if __name__
== "__main__":
183 unittest
.main(exit
=False)
184 suite
= unittest
.TestSuite()
185 #suite.addTest(TestRunner(HelloTestCases.test_data))
186 suite
.addTest(TestRunner(AttnTestCase
.test_data
))
187 suite
.addTest(TestRunner(GeneralTestCases
.test_data
))
188 suite
.addTest(TestRunner(LDSTTestCase
.test_data
))
189 #suite.addTest(TestRunner(CRTestCase.test_data))
190 #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
191 #suite.addTest(TestRunner(LogicalTestCase.test_data))
192 #suite.addTest(TestRunner(ALUTestCase.test_data))
193 #suite.addTest(TestRunner(BranchTestCase.test_data))
194 #suite.addTest(TestRunner(SPRTestCase.test_data))
196 runner
= unittest
.TextTestRunner()