1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
, ClockSignal
9 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
10 # Also, check out the cxxsim nmigen branch, and latest yosys from git
11 from nmutil
.sim_tmp_alternative
import Simulator
, Settle
13 from nmutil
.formaltest
import FHDLTestCase
14 from nmigen
.cli
import rtlil
16 from soc
.decoder
.isa
.caller
import special_sprs
17 from soc
.decoder
.isa
.all
import ISA
18 from soc
.decoder
.power_enums
import Function
, XER_bits
19 from soc
.config
.endian
import bigendian
21 from soc
.decoder
.power_decoder
import create_pdecode
22 from soc
.decoder
.power_decoder2
import PowerDecode2
24 from soc
.simple
.issuer
import TestIssuerInternal
25 from soc
.experiment
.compalu_multi
import find_ok
# hack
27 from soc
.config
.test
.test_loadstore
import TestMemPspec
28 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
31 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
33 from soc
.debug
.dmi
import DBGCore
, DBGCtrl
, DBGStat
35 # test with ALU data and Logical data
36 from soc
.fu
.alu
.test
.test_pipe_caller
import ALUTestCase
37 from soc
.fu
.div
.test
.test_pipe_caller
import DivTestCases
38 from soc
.fu
.logical
.test
.test_pipe_caller
import LogicalTestCase
39 from soc
.fu
.shift_rot
.test
.test_pipe_caller
import ShiftRotTestCase
40 from soc
.fu
.cr
.test
.test_pipe_caller
import CRTestCase
41 #from soc.fu.branch.test.test_pipe_caller import BranchTestCase
42 #from soc.fu.spr.test.test_pipe_caller import SPRTestCase
43 from soc
.fu
.ldst
.test
.test_pipe_caller
import LDSTTestCase
44 from soc
.simulator
.test_sim
import (GeneralTestCases
, AttnTestCase
)
45 #from soc.simulator.test_helloworld_sim import HelloTestCases
48 def setup_i_memory(imem
, startaddr
, instructions
):
50 print("insn before, init mem", mem
.depth
, mem
.width
, mem
,
52 for i
in range(mem
.depth
):
53 yield mem
._array
[i
].eq(0)
55 startaddr
//= 4 # instructions are 32-bit
58 for ins
in instructions
:
59 if isinstance(ins
, tuple):
63 insn
= insn
& 0xffffffff
64 yield mem
._array
[startaddr
].eq(insn
)
67 print("instr: %06x 0x%x %s" % (4*startaddr
, insn
, code
))
69 startaddr
= startaddr
& mask
74 for ins
in instructions
:
75 if isinstance(ins
, tuple):
79 insn
= insn
& 0xffffffff
80 msbs
= (startaddr
>> 1) & mask
81 val
= yield mem
._array
[msbs
]
83 print("before set", hex(4*startaddr
),
84 hex(msbs
), hex(val
), hex(insn
))
85 lsb
= 1 if (startaddr
& 1) else 0
86 val
= (val |
(insn
<< (lsb
*32)))
88 yield mem
._array
[msbs
].eq(val
)
91 print("after set", hex(4*startaddr
), hex(msbs
), hex(val
))
92 print("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
94 startaddr
= startaddr
& mask
97 def set_dmi(dmi
, addr
, data
):
99 yield dmi
.addr_i
.eq(addr
)
100 yield dmi
.din
.eq(data
)
103 ack
= yield dmi
.ack_o
108 yield dmi
.req_i
.eq(0)
109 yield dmi
.addr_i
.eq(0)
115 def get_dmi(dmi
, addr
):
116 yield dmi
.req_i
.eq(1)
117 yield dmi
.addr_i
.eq(addr
)
121 ack
= yield dmi
.ack_o
126 data
= yield dmi
.dout
# get data after ack valid for 1 cycle
127 yield dmi
.req_i
.eq(0)
128 yield dmi
.addr_i
.eq(0)
134 class TestRunner(FHDLTestCase
):
135 def __init__(self
, tst_data
):
136 super().__init
__("run_all")
137 self
.test_data
= tst_data
144 pspec
= TestMemPspec(ldst_ifacetype
='test_bare_wb',
145 imem_ifacetype
='test_bare_wb',
155 m
.submodules
.issuer
= issuer
= TestIssuerInternal(pspec
)
156 imem
= issuer
.imem
._get
_memory
()
159 pdecode2
= issuer
.pdecode2
162 # copy of the decoder for simulator
163 simdec
= create_pdecode()
164 simdec2
= PowerDecode2(simdec
)
165 m
.submodules
.simdec2
= simdec2
# pain in the neck
167 # run core clock at same rate as test clock
168 intclk
= ClockSignal("coresync")
169 comb
+= intclk
.eq(ClockSignal())
171 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
180 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
184 for test
in self
.test_data
:
187 #yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
189 # set up bigendian (TODO: don't do this, use MSR)
190 yield issuer
.core_bigendian_i
.eq(bigendian
)
199 program
= test
.program
200 self
.subTest(test
.name
)
201 print("regs", test
.regs
)
202 print("sprs", test
.sprs
)
204 print("mem", test
.mem
)
205 print("msr", test
.msr
)
206 print("assem", program
.assembly
)
207 gen
= list(program
.generate_instructions())
208 insncode
= program
.assembly
.splitlines()
209 instructions
= list(zip(gen
, insncode
))
210 sim
= ISA(simdec2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
212 initial_insns
=gen
, respect_pc
=True,
213 disassembly
=insncode
,
216 pc
= 0 # start address
217 counter
= 0 # test to pause/start
219 yield from setup_i_memory(imem
, pc
, instructions
)
220 yield from setup_test_memory(l0
, sim
)
221 yield from setup_regs(pdecode2
, core
, test
)
224 yield issuer
.pc_i
.ok
.eq(1)
227 print("instructions", instructions
)
229 index
= sim
.pc
.CIA
.value
//4
230 while index
< len(instructions
):
231 ins
, code
= instructions
[index
]
233 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
239 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.START
)
240 yield issuer
.pc_i
.ok
.eq(0) # no change PC after this
244 counter
= counter
+ 1
246 # wait until executed
247 yield from wait_for_busy_hi(core
)
248 yield from wait_for_busy_clear(core
)
250 # set up simulated instruction (in simdec2)
252 yield from sim
.setup_one()
253 except KeyError: # indicates instruction not in imem: stop
257 # call simulated operation
259 yield from sim
.execute_one()
261 index
= sim
.pc
.CIA
.value
//4
263 terminated
= yield issuer
.dbg
.terminated_o
264 print("terminated", terminated
)
266 if index
>= len(instructions
):
267 print ("index over, send dmi stop")
269 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
273 # wait one cycle for registers to settle
277 yield from check_regs(self
, sim
, core
, test
, code
)
280 yield from check_sim_memory(self
, l0
, sim
, code
)
282 terminated
= yield issuer
.dbg
.terminated_o
283 print("terminated(2)", terminated
)
288 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
293 cr
= yield from get_dmi(dmi
, DBGCore
.CR
)
294 print ("after test %s cr value %x" % (test
.name
, cr
))
297 xer
= yield from get_dmi(dmi
, DBGCore
.XER
)
298 print ("after test %s XER value %x" % (test
.name
, xer
))
300 # test of dmi reg get
301 for int_reg
in range(32):
302 yield from set_dmi(dmi
, DBGCore
.GSPR_IDX
, int_reg
)
303 value
= yield from get_dmi(dmi
, DBGCore
.GSPR_DATA
)
305 print ("after test %s reg %2d value %x" % \
306 (test
.name
, int_reg
, value
))
308 sim
.add_sync_process(process
)
309 with sim
.write_vcd("issuer_simulator.vcd",
314 if __name__
== "__main__":
315 unittest
.main(exit
=False)
316 suite
= unittest
.TestSuite()
317 # suite.addTest(TestRunner(HelloTestCases.test_data))
318 #suite.addTest(TestRunner(DivTestCases().test_data))
319 # suite.addTest(TestRunner(AttnTestCase.test_data))
320 #suite.addTest(TestRunner(GeneralTestCases.test_data))
321 #suite.addTest(TestRunner(LDSTTestCase().test_data))
322 #suite.addTest(TestRunner(CRTestCase().test_data))
323 #suite.addTest(TestRunner(ShiftRotTestCase().test_data))
324 #suite.addTest(TestRunner(LogicalTestCase().test_data))
325 suite
.addTest(TestRunner(ALUTestCase().test_data
))
326 # suite.addTest(TestRunner(BranchTestCase.test_data))
327 # suite.addTest(TestRunner(SPRTestCase.test_data))
329 runner
= unittest
.TextTestRunner()