1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
8 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
9 from nmutil
.formaltest
import FHDLTestCase
10 from nmigen
.cli
import rtlil
12 from soc
.decoder
.isa
.caller
import special_sprs
13 from soc
.decoder
.isa
.all
import ISA
14 from soc
.decoder
.power_enums
import Function
, XER_bits
17 from soc
.simple
.issuer
import TestIssuer
18 from soc
.experiment
.compalu_multi
import find_ok
# hack
20 from soc
.config
.test
.test_loadstore
import TestMemPspec
21 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
24 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
27 # test with ALU data and Logical data
28 #from soc.fu.alu.test.test_pipe_caller import ALUTestCase
29 #from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
30 #from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
31 #from soc.fu.cr.test.test_pipe_caller import CRTestCase
32 #from soc.fu.branch.test.test_pipe_caller import BranchTestCase
33 from soc
.fu
.spr
.test
.test_pipe_caller
import SPRTestCase
34 #from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
35 #from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
36 #from soc.simulator.test_helloworld_sim import HelloTestCases
39 def setup_i_memory(imem
, startaddr
, instructions
):
41 print ("insn before, init mem", mem
.depth
, mem
.width
, mem
,
43 for i
in range(mem
.depth
):
44 yield mem
._array
[i
].eq(0)
46 startaddr
//= 4 # instructions are 32-bit
48 for ins
in instructions
:
49 if isinstance(ins
, tuple):
53 msbs
= (startaddr
>>1) & mask
54 val
= yield mem
._array
[msbs
]
56 print ("before set", hex(4*startaddr
),
57 hex(msbs
), hex(val
), hex(insn
))
58 lsb
= 1 if (startaddr
& 1) else 0
59 val
= (val |
(insn
<< (lsb
*32))) & mask
60 yield mem
._array
[msbs
].eq(val
)
63 print ("after set", hex(4*startaddr
), hex(msbs
), hex(val
))
64 print ("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
66 startaddr
= startaddr
& mask
69 class TestRunner(FHDLTestCase
):
70 def __init__(self
, tst_data
):
71 super().__init
__("run_all")
72 self
.test_data
= tst_data
80 pspec
= TestMemPspec(ldst_ifacetype
='test_bare_wb',
81 imem_ifacetype
='test_bare_wb',
85 m
.submodules
.issuer
= issuer
= TestIssuer(pspec
)
86 imem
= issuer
.imem
._get
_memory
()
88 pdecode2
= core
.pdecode2
91 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
92 comb
+= issuer
.go_insn_i
.eq(go_insn_i
)
100 for test
in self
.test_data
:
103 yield core
.bigendian_i
.eq(1)
104 yield core
.core_start_i
.eq(1)
106 yield core
.core_start_i
.eq(0)
110 program
= test
.program
111 self
.subTest(test
.name
)
112 print ("regs", test
.regs
)
113 print ("sprs", test
.sprs
)
114 print ("cr", test
.cr
)
115 print ("mem", test
.mem
)
116 print ("msr", test
.msr
)
117 print ("assem", program
.assembly
)
118 gen
= list(program
.generate_instructions())
119 insncode
= program
.assembly
.splitlines()
120 instructions
= list(zip(gen
, insncode
))
121 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
123 initial_insns
=gen
, respect_pc
=True,
124 disassembly
=insncode
)
126 pc
= 0 # start address
128 yield from setup_i_memory(imem
, pc
, instructions
)
129 yield from setup_test_memory(l0
, sim
)
130 yield from setup_regs(core
, test
)
133 yield issuer
.pc_i
.ok
.eq(1)
135 index
= sim
.pc
.CIA
.value
//4
136 while index
< len(instructions
):
137 ins
, code
= instructions
[index
]
139 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
142 # start the instruction
143 yield go_insn_i
.eq(1)
145 yield issuer
.pc_i
.ok
.eq(0) # don't change PC from now on
146 yield go_insn_i
.eq(0) # and don't issue a new insn
149 # wait until executed
150 yield from wait_for_busy_hi(core
)
151 yield from wait_for_busy_clear(core
)
153 terminated
= yield core
.core_terminated_o
154 print ("terminated", terminated
)
157 # call simulated operation
158 opname
= code
.split(' ')[0]
159 yield from sim
.call(opname
)
161 index
= sim
.pc
.CIA
.value
//4
164 yield from check_regs(self
, sim
, core
, test
, code
)
167 yield from check_sim_memory(self
, l0
, sim
, code
)
169 terminated
= yield core
.core_terminated_o
173 sim
.add_sync_process(process
)
174 with sim
.write_vcd("issuer_simulator.vcd",
179 if __name__
== "__main__":
180 unittest
.main(exit
=False)
181 suite
= unittest
.TestSuite()
182 #suite.addTest(TestRunner(HelloTestCases.test_data))
183 #suite.addTest(TestRunner(AttnTestCase.test_data))
184 #suite.addTest(TestRunner(GeneralTestCases.test_data))
185 #suite.addTest(TestRunner(LDSTTestCase.test_data))
186 #suite.addTest(TestRunner(CRTestCase.test_data))
187 #suite.addTest(TestRunner(ShiftRotTestCase.test_data))
188 #suite.addTest(TestRunner(LogicalTestCase.test_data))
189 #suite.addTest(TestRunner(ALUTestCase.test_data))
190 #suite.addTest(TestRunner(BranchTestCase.test_data))
191 suite
.addTest(TestRunner(SPRTestCase
.test_data
))
193 runner
= unittest
.TextTestRunner()