src/soc/simple/test/test_issuer.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7
   8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
   9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  10
  11 import unittest
  12 from soc.simple.test.test_runner import TestRunner
  13
  14 # test with ALU data and Logical data
  15 from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  16 from soc.fu.div.test.test_pipe_caller import DivTestCases
  17 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  18 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  19 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  20 # from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  21 # from soc.fu.spr.test.test_pipe_caller import SPRTestCase
  22 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  23 from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
  24 # from soc.simulator.test_helloworld_sim import HelloTestCases
  25
  26
  27 if __name__ == "__main__":
  28     unittest.main(exit=False)
  29     suite = unittest.TestSuite()
  30     # suite.addTest(TestRunner(HelloTestCases.test_data))
  31     suite.addTest(TestRunner(DivTestCases().test_data))
  32     # suite.addTest(TestRunner(AttnTestCase.test_data))
  33     suite.addTest(TestRunner(GeneralTestCases.test_data))
  34     suite.addTest(TestRunner(LDSTTestCase().test_data))
  35     suite.addTest(TestRunner(CRTestCase().test_data))
  36     suite.addTest(TestRunner(ShiftRotTestCase().test_data))
  37     suite.addTest(TestRunner(LogicalTestCase().test_data))
  38     suite.addTest(TestRunner(ALUTestCase().test_data))
  39     # suite.addTest(TestRunner(BranchTestCase.test_data))
  40     # suite.addTest(TestRunner(SPRTestCase.test_data))
  41
  42     runner = unittest.TextTestRunner()
  43     runner.run(suite)