src/soc/simple/test/test_issuer.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7 from nmigen import Module, Signal, Cat
   8 from nmigen.back.pysim import Simulator, Delay, Settle
   9 from nmutil.formaltest import FHDLTestCase
  10 from nmigen.cli import rtlil
  11 import unittest
  12 from soc.decoder.isa.caller import special_sprs
  13 from soc.decoder.isa.all import ISA
  14 from soc.decoder.power_enums import Function, XER_bits
  15 from soc.config.endian import bigendian
  16
  17 from soc.simple.issuer import TestIssuer
  18 from soc.experiment.compalu_multi import find_ok  # hack
  19
  20 from soc.config.test.test_loadstore import TestMemPspec
  21 from soc.simple.test.test_core import (setup_regs, check_regs,
  22                                        wait_for_busy_clear,
  23                                        wait_for_busy_hi)
  24 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  25                                                  check_sim_memory)
  26 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
  27
  28 # test with ALU data and Logical data
  29 #from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  30 #from soc.fu.div.test.test_pipe_caller import DivTestCase
  31 #from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
  32 #from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
  33 from soc.fu.cr.test.test_pipe_caller import CRTestCase
  34 #from soc.fu.branch.test.test_pipe_caller import BranchTestCase
  35 #from soc.fu.spr.test.test_pipe_caller import SPRTestCase
  36 from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
  37 from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
  38 #from soc.simulator.test_helloworld_sim import HelloTestCases
  39
  40
  41 def setup_i_memory(imem, startaddr, instructions):
  42     mem = imem
  43     print("insn before, init mem", mem.depth, mem.width, mem,
  44           len(instructions))
  45     for i in range(mem.depth):
  46         yield mem._array[i].eq(0)
  47     yield Settle()
  48     startaddr //= 4  # instructions are 32-bit
  49     if mem.width == 32:
  50         mask = ((1 << 32)-1)
  51         for ins in instructions:
  52             if isinstance(ins, tuple):
  53                 insn, code = ins
  54             else:
  55                 insn, code = ins, ''
  56             insn = insn & 0xffffffff
  57             yield mem._array[startaddr].eq(insn)
  58             yield Settle()
  59             if insn != 0:
  60                 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  61             startaddr += 1
  62             startaddr = startaddr & mask
  63         return
  64
  65     # 64 bit
  66     mask = ((1 << 64)-1)
  67     for ins in instructions:
  68         if isinstance(ins, tuple):
  69             insn, code = ins
  70         else:
  71             insn, code = ins, ''
  72         insn = insn & 0xffffffff
  73         msbs = (startaddr >> 1) & mask
  74         val = yield mem._array[msbs]
  75         if insn != 0:
  76             print("before set", hex(4*startaddr),
  77                   hex(msbs), hex(val), hex(insn))
  78         lsb = 1 if (startaddr & 1) else 0
  79         val = (val | (insn << (lsb*32)))
  80         val = val & mask
  81         yield mem._array[msbs].eq(val)
  82         yield Settle()
  83         if insn != 0:
  84             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  85             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  86         startaddr += 1
  87         startaddr = startaddr & mask
  88
  89
  90 def set_dmi(dmi, addr, data):
  91     yield dmi.req_i.eq(1)
  92     yield dmi.addr_i.eq(addr)
  93     yield dmi.din.eq(data)
  94     yield dmi.we_i.eq(1)
  95     while True:
  96         ack = yield dmi.ack_o
  97         if ack:
  98             break
  99         yield
 100     yield dmi.req_i.eq(0)
 101     yield dmi.addr_i.eq(0)
 102     yield dmi.din.eq(0)
 103     yield dmi.we_i.eq(0)
 104
 105
 106 class TestRunner(FHDLTestCase):
 107     def __init__(self, tst_data):
 108         super().__init__("run_all")
 109         self.test_data = tst_data
 110
 111     def run_all(self):
 112         m = Module()
 113         comb = m.d.comb
 114         pc_i = Signal(32)
 115
 116         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
 117                              imem_ifacetype='test_bare_wb',
 118                              addr_wid=48,
 119                              mask_wid=8,
 120                              imem_reg_wid=64,
 121                              reg_wid=64)
 122         m.submodules.issuer = issuer = TestIssuer(pspec)
 123         imem = issuer.imem._get_memory()
 124         core = issuer.core
 125         dmi = issuer.dbg.dmi
 126         pdecode2 = core.pdecode2
 127         l0 = core.l0
 128
 129         comb += issuer.pc_i.data.eq(pc_i)
 130
 131         # nmigen Simulation
 132         sim = Simulator(m)
 133         sim.add_clock(1e-6)
 134
 135         def process():
 136
 137             # start in stopped
 138             yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 139             yield
 140             yield
 141
 142             for test in self.test_data:
 143
 144                 # pull a reset
 145                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 146
 147                 # set up bigendian (TODO: don't do this, use MSR)
 148                 yield issuer.core_bigendian_i.eq(bigendian)
 149                 yield Settle()
 150
 151                 yield
 152                 yield
 153                 yield
 154                 yield
 155
 156                 print(test.name)
 157                 program = test.program
 158                 self.subTest(test.name)
 159                 print("regs", test.regs)
 160                 print("sprs", test.sprs)
 161                 print("cr", test.cr)
 162                 print("mem", test.mem)
 163                 print("msr", test.msr)
 164                 print("assem", program.assembly)
 165                 gen = list(program.generate_instructions())
 166                 insncode = program.assembly.splitlines()
 167                 instructions = list(zip(gen, insncode))
 168                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
 169                           test.msr,
 170                           initial_insns=gen, respect_pc=True,
 171                           disassembly=insncode,
 172                           bigendian=bigendian)
 173
 174                 pc = 0  # start address
 175                 counter = 0 # test to pause/start
 176
 177                 yield from setup_i_memory(imem, pc, instructions)
 178                 yield from setup_test_memory(l0, sim)
 179                 yield from setup_regs(core, test)
 180
 181                 yield pc_i.eq(pc)
 182                 yield issuer.pc_i.ok.eq(1)
 183
 184                 print("instructions", instructions)
 185
 186                 index = sim.pc.CIA.value//4
 187                 while index < len(instructions):
 188                     ins, code = instructions[index]
 189
 190                     print("instruction: 0x{:X}".format(ins & 0xffffffff))
 191                     print(index, code)
 192
 193                     if counter == 0:
 194                         # start the core
 195                         yield
 196                         yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.START)
 197                         yield issuer.pc_i.ok.eq(0)  # no change PC after this
 198                         yield
 199                         yield
 200
 201                     counter = counter + 1
 202
 203                     # wait until executed
 204                     yield from wait_for_busy_hi(core)
 205                     yield from wait_for_busy_clear(core)
 206
 207                     terminated = yield issuer.dbg.terminated_o
 208                     print("terminated", terminated)
 209
 210                     print("sim", code)
 211                     # call simulated operation
 212                     opname = code.split(' ')[0]
 213                     yield from sim.call(opname)
 214                     yield Settle()
 215                     index = sim.pc.CIA.value//4
 216
 217                     # register check
 218                     yield from check_regs(self, sim, core, test, code)
 219
 220                     # Memory check
 221                     yield from check_sim_memory(self, l0, sim, code)
 222
 223                     terminated = yield issuer.dbg.terminated_o
 224                     if terminated:
 225                         break
 226
 227         sim.add_sync_process(process)
 228         with sim.write_vcd("issuer_simulator.vcd",
 229                            traces=[]):
 230             sim.run()
 231
 232
 233 if __name__ == "__main__":
 234     unittest.main(exit=False)
 235     suite = unittest.TestSuite()
 236     # suite.addTest(TestRunner(HelloTestCases.test_data))
 237     # suite.addTest(TestRunner(DivTestCase.test_data))
 238     # suite.addTest(TestRunner(AttnTestCase.test_data))
 239     suite.addTest(TestRunner(GeneralTestCases.test_data))
 240     # suite.addTest(TestRunner(LDSTTestCase().test_data))
 241     # suite.addTest(TestRunner(CRTestCase().test_data))
 242     # suite.addTest(TestRunner(ShiftRotTestCase.test_data))
 243     # suite.addTest(TestRunner(LogicalTestCase.test_data))
 244     # suite.addTest(TestRunner(ALUTestCase.test_data))
 245     # suite.addTest(TestRunner(BranchTestCase.test_data))
 246     # suite.addTest(TestRunner(SPRTestCase.test_data))
 247
 248     runner = unittest.TextTestRunner()
 249     runner.run(suite)