1 """simple core test, runs instructions from a TestMemory
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
7 from nmigen
import Module
, Signal
, Cat
8 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
9 from nmutil
.formaltest
import FHDLTestCase
10 from nmigen
.cli
import rtlil
12 from soc
.decoder
.isa
.caller
import special_sprs
13 from soc
.decoder
.isa
.all
import ISA
14 from soc
.decoder
.power_enums
import Function
, XER_bits
15 from soc
.config
.endian
import bigendian
17 from soc
.simple
.issuer
import TestIssuer
18 from soc
.experiment
.compalu_multi
import find_ok
# hack
20 from soc
.config
.test
.test_loadstore
import TestMemPspec
21 from soc
.simple
.test
.test_core
import (setup_regs
, check_regs
,
24 from soc
.fu
.compunits
.test
.test_compunit
import (setup_test_memory
,
26 from soc
.debug
.dmi
import DBGCore
, DBGCtrl
, DBGStat
28 # test with ALU data and Logical data
29 #from soc.fu.alu.test.test_pipe_caller import ALUTestCase
30 #from soc.fu.div.test.test_pipe_caller import DivTestCase
31 #from soc.fu.logical.test.test_pipe_caller import LogicalTestCase
32 #from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
33 from soc
.fu
.cr
.test
.test_pipe_caller
import CRTestCase
34 #from soc.fu.branch.test.test_pipe_caller import BranchTestCase
35 #from soc.fu.spr.test.test_pipe_caller import SPRTestCase
36 from soc
.fu
.ldst
.test
.test_pipe_caller
import LDSTTestCase
37 from soc
.simulator
.test_sim
import (GeneralTestCases
, AttnTestCase
)
38 #from soc.simulator.test_helloworld_sim import HelloTestCases
41 def setup_i_memory(imem
, startaddr
, instructions
):
43 print("insn before, init mem", mem
.depth
, mem
.width
, mem
,
45 for i
in range(mem
.depth
):
46 yield mem
._array
[i
].eq(0)
48 startaddr
//= 4 # instructions are 32-bit
51 for ins
in instructions
:
52 if isinstance(ins
, tuple):
56 insn
= insn
& 0xffffffff
57 yield mem
._array
[startaddr
].eq(insn
)
60 print("instr: %06x 0x%x %s" % (4*startaddr
, insn
, code
))
62 startaddr
= startaddr
& mask
67 for ins
in instructions
:
68 if isinstance(ins
, tuple):
72 insn
= insn
& 0xffffffff
73 msbs
= (startaddr
>> 1) & mask
74 val
= yield mem
._array
[msbs
]
76 print("before set", hex(4*startaddr
),
77 hex(msbs
), hex(val
), hex(insn
))
78 lsb
= 1 if (startaddr
& 1) else 0
79 val
= (val |
(insn
<< (lsb
*32)))
81 yield mem
._array
[msbs
].eq(val
)
84 print("after set", hex(4*startaddr
), hex(msbs
), hex(val
))
85 print("instr: %06x 0x%x %s %08x" % (4*startaddr
, insn
, code
, val
))
87 startaddr
= startaddr
& mask
90 def set_dmi(dmi
, addr
, data
):
92 yield dmi
.addr_i
.eq(addr
)
93 yield dmi
.din
.eq(data
)
100 yield dmi
.req_i
.eq(0)
101 yield dmi
.addr_i
.eq(0)
106 def get_dmi(dmi
, addr
):
107 yield dmi
.req_i
.eq(1)
108 yield dmi
.addr_i
.eq(addr
)
112 ack
= yield dmi
.ack_o
117 data
= yield dmi
.dout
# get data after ack valid for 1 cycle
118 yield dmi
.req_i
.eq(0)
119 yield dmi
.addr_i
.eq(0)
124 class TestRunner(FHDLTestCase
):
125 def __init__(self
, tst_data
):
126 super().__init
__("run_all")
127 self
.test_data
= tst_data
134 pspec
= TestMemPspec(ldst_ifacetype
='test_bare_wb',
135 imem_ifacetype
='test_bare_wb',
140 m
.submodules
.issuer
= issuer
= TestIssuer(pspec
)
141 imem
= issuer
.imem
._get
_memory
()
144 pdecode2
= core
.pdecode2
147 comb
+= issuer
.pc_i
.data
.eq(pc_i
)
156 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.STOP
)
160 for test
in self
.test_data
:
163 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.RESET
)
165 # set up bigendian (TODO: don't do this, use MSR)
166 yield issuer
.core_bigendian_i
.eq(bigendian
)
175 program
= test
.program
176 self
.subTest(test
.name
)
177 print("regs", test
.regs
)
178 print("sprs", test
.sprs
)
180 print("mem", test
.mem
)
181 print("msr", test
.msr
)
182 print("assem", program
.assembly
)
183 gen
= list(program
.generate_instructions())
184 insncode
= program
.assembly
.splitlines()
185 instructions
= list(zip(gen
, insncode
))
186 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
188 initial_insns
=gen
, respect_pc
=True,
189 disassembly
=insncode
,
192 pc
= 0 # start address
193 counter
= 0 # test to pause/start
195 yield from setup_i_memory(imem
, pc
, instructions
)
196 yield from setup_test_memory(l0
, sim
)
197 yield from setup_regs(core
, test
)
200 yield issuer
.pc_i
.ok
.eq(1)
202 print("instructions", instructions
)
204 index
= sim
.pc
.CIA
.value
//4
205 while index
< len(instructions
):
206 ins
, code
= instructions
[index
]
208 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
214 yield from set_dmi(dmi
, DBGCore
.CTRL
, 1<<DBGCtrl
.START
)
215 yield issuer
.pc_i
.ok
.eq(0) # no change PC after this
219 counter
= counter
+ 1
221 # wait until executed
222 yield from wait_for_busy_hi(core
)
223 yield from wait_for_busy_clear(core
)
225 terminated
= yield issuer
.dbg
.terminated_o
226 print("terminated", terminated
)
229 # call simulated operation
230 opname
= code
.split(' ')[0]
231 yield from sim
.call(opname
)
233 index
= sim
.pc
.CIA
.value
//4
236 yield from check_regs(self
, sim
, core
, test
, code
)
239 yield from check_sim_memory(self
, l0
, sim
, code
)
241 terminated
= yield issuer
.dbg
.terminated_o
245 # test of dmi reg get
247 yield from set_dmi(dmi
, DBGCore
.GSPR_IDX
, int_reg
) # int reg 9
248 value
= yield from get_dmi(dmi
, DBGCore
.GSPR_DATA
) # get data
250 print ("after test %s reg %x value %s" % \
251 (test
.name
, int_reg
, value
))
253 sim
.add_sync_process(process
)
254 with sim
.write_vcd("issuer_simulator.vcd",
259 if __name__
== "__main__":
260 unittest
.main(exit
=False)
261 suite
= unittest
.TestSuite()
262 # suite.addTest(TestRunner(HelloTestCases.test_data))
263 # suite.addTest(TestRunner(DivTestCase.test_data))
264 # suite.addTest(TestRunner(AttnTestCase.test_data))
265 suite
.addTest(TestRunner(GeneralTestCases
.test_data
))
266 # suite.addTest(TestRunner(LDSTTestCase().test_data))
267 # suite.addTest(TestRunner(CRTestCase().test_data))
268 # suite.addTest(TestRunner(ShiftRotTestCase.test_data))
269 # suite.addTest(TestRunner(LogicalTestCase.test_data))
270 # suite.addTest(TestRunner(ALUTestCase.test_data))
271 # suite.addTest(TestRunner(BranchTestCase.test_data))
272 # suite.addTest(TestRunner(SPRTestCase.test_data))
274 runner
= unittest
.TextTestRunner()