raise interrupt on misaligned atomic LDST
[soc.git] / src / soc / simple / test / test_issuer_svp64.py
1 """test of SVP64 operations.
2
3 related bugs:
4
5 * https://bugs.libre-soc.org/show_bug.cgi?id=363
6 """
7
8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
10
11 import unittest
12 from soc.simple.test.test_runner import TestRunner
13
14 # test with ALU data and Logical data
15 from openpower.test.alu.svp64_cases import SVP64ALUTestCase
16 from openpower.test.logical.svp64_cases import SVP64LogicalTestCase
17
18
19 if __name__ == "__main__":
20 unittest.main(exit=False)
21 suite = unittest.TestSuite()
22 suite.addTest(TestRunner(SVP64ALUTestCase().test_data))
23 suite.addTest(TestRunner(SVP64LogicalTestCase().test_data))
24
25 runner = unittest.TextTestRunner()
26 runner.run(suite)