src/soc/simple/test/test_microwatt.py

   1 from soc.simulator.program import Program
   2 from soc.fu.test.common import TestCase
   3
   4 import unittest
   5
   6 from nmigen import Module, Signal
   7 from nmigen.back.pysim import Simulator, Delay, Settle
   8 from nmutil.formaltest import FHDLTestCase
   9
  10 from soc.simple.issuer import TestIssuer
  11
  12 from soc.config.test.test_loadstore import TestMemPspec
  13 from soc.simple.test.test_core import (setup_regs, check_regs,
  14                                        wait_for_busy_clear,
  15                                        wait_for_busy_hi)
  16 from soc.fu.compunits.test.test_compunit import (setup_test_memory,
  17                                                  check_sim_memory,
  18                                                  get_l0_mem)
  19
  20 from soc.simple.test.test_issuer import setup_i_memory
  21
  22 import sys
  23 sys.setrecursionlimit(10**6)
  24
  25
  26 class BinaryTestCase(FHDLTestCase):
  27     test_data = []
  28
  29     def __init__(self, name="general"):
  30         super().__init__(name)
  31         self.test_name = name
  32
  33     @unittest.skip("a bit big")
  34     def test_binary(self):
  35         with Program("1.bin") as program:
  36             self.run_tst_program(program)
  37
  38     def test_binary(self):
  39         with Program("hello_world.bin") as program:
  40             self.run_tst_program(program)
  41
  42     def run_tst_program(self, prog):
  43         initial_regs = [0] * 32
  44         tc = TestCase(prog, self.test_name, initial_regs, None, 0,
  45                                             None, 0,
  46                       do_sim=False)
  47         self.test_data.append(tc)
  48
  49
  50 class TestRunner(FHDLTestCase):
  51     def __init__(self, tst_data):
  52         super().__init__("binary_runner")
  53         self.test_data = tst_data
  54
  55     def binary_runner(self):
  56         m = Module()
  57         comb = m.d.comb
  58         go_insn_i = Signal()
  59         pc_i = Signal(32)
  60
  61         pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
  62                              imem_ifacetype='test_bare_wb',
  63                              addr_wid=48,
  64                              mask_wid=8,
  65                              reg_wid=64,
  66                              imem_test_depth=32768,
  67                              dmem_test_depth=32768)
  68         m.submodules.issuer = issuer = TestIssuer(pspec)
  69         imem = issuer.imem._get_memory()
  70         core = issuer.core
  71         pdecode2 = core.pdecode2
  72         l0 = core.l0
  73
  74         comb += issuer.pc_i.data.eq(pc_i)
  75         comb += issuer.go_insn_i.eq(go_insn_i)
  76
  77         # nmigen Simulation
  78         sim = Simulator(m)
  79         sim.add_clock(1e-6)
  80
  81         def process():
  82
  83             for test in self.test_data:
  84
  85                 # get core going
  86                 yield core.bigendian_i.eq(1)
  87                 yield core.core_start_i.eq(1)
  88                 yield
  89                 yield core.core_start_i.eq(0)
  90                 yield Settle()
  91
  92                 print(test.name)
  93                 program = test.program
  94                 self.subTest(test.name)
  95                 print ("regs", test.regs)
  96                 print ("sprs", test.sprs)
  97                 print ("cr", test.cr)
  98                 print ("mem", test.mem)
  99                 print ("msr", test.msr)
 100                 print ("assem", program.assembly)
 101                 instructions = list(program.generate_instructions())
 102
 103                 print ("instructions", len(instructions))
 104
 105                 pc = 0 # start of memory
 106
 107                 yield from setup_i_memory(imem, pc, instructions)
 108                 # blech!  put the same listing into the data memory
 109                 data_mem = get_l0_mem(l0)
 110                 yield from setup_i_memory(data_mem, pc, instructions)
 111                 #yield from setup_test_memory(l0, sim)
 112                 yield from setup_regs(core, test)
 113
 114                 yield pc_i.eq(pc)
 115                 yield issuer.pc_i.ok.eq(1)
 116
 117                 while True:
 118
 119                     # start the instruction
 120                     yield go_insn_i.eq(1)
 121                     yield
 122                     yield issuer.pc_i.ok.eq(0) # don't change PC from now on
 123                     yield go_insn_i.eq(0)      # and don't issue a new insn
 124                     yield from wait_for_busy_hi(core)
 125                     yield Settle()
 126
 127                     # wait until executed
 128                     ins = yield core.raw_opcode_i
 129                     pc = yield issuer.pc_o
 130                     print("instruction: 0x%x @ %x" % (ins & 0xffffffff, pc))
 131                     yield from wait_for_busy_clear(core)
 132
 133                     terminated = yield core.core_terminated_o
 134                     print ("terminated", terminated)
 135
 136                     terminated = yield core.core_terminated_o
 137                     if terminated:
 138                         break
 139
 140             # register check
 141             #yield from check_regs(self, sim, core, test, code)
 142
 143             # Memory check
 144             #yield from check_sim_memory(self, l0, sim, code)
 145
 146         sim.add_sync_process(process)
 147         with sim.write_vcd("binary_issuer_simulator.vcd",
 148                             traces=[]):
 149             sim.run()
 150
 151
 152 if __name__ == "__main__":
 153     unittest.main(exit=False)
 154     suite = unittest.TestSuite()
 155     suite.addTest(TestRunner(BinaryTestCase.test_data))
 156
 157     runner = unittest.TextTestRunner()
 158     runner.run(suite)
 159