1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.test
.utils
import FHDLTestCase
5 from soc
.decoder
.power_decoder
import (create_pdecode
)
6 from soc
.decoder
.power_enums
import (Function
, InternalOp
,
7 In1Sel
, In2Sel
, In3Sel
,
8 OutSel
, RC
, LdstLen
, CryIn
,
9 single_bit_flags
, Form
, SPR
,
10 get_signal_name
, get_csv
)
11 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
12 from soc
.simulator
.program
import Program
13 from soc
.simulator
.qemu
import run_program
14 from soc
.decoder
.isa
.all
import ISA
18 def __init__(self
, num
):
22 class DecoderTestCase(FHDLTestCase
):
24 def run_tst(self
, generator
, initial_mem
=None):
27 instruction
= Signal(32)
29 pdecode
= create_pdecode()
31 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
33 simulator
= ISA(pdecode2
, [0] * 32, {}, 0, initial_mem
, 0)
34 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
35 comb
+= pdecode2
.dec
.bigendian
.eq(0)
36 gen
= generator
.generate_instructions()
37 instructions
= list(zip(gen
, generator
.assembly
.splitlines()))
42 index
= simulator
.pc
.CIA
.value
//4
43 while index
< len(instructions
):
44 ins
, code
= instructions
[index
]
46 print("0x{:X}".format(ins
& 0xffffffff))
49 yield instruction
.eq(ins
)
52 opname
= code
.split(' ')[0]
53 yield from simulator
.call(opname
)
54 index
= simulator
.pc
.CIA
.value
//4
57 sim
.add_process(process
)
58 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
64 @unittest.skip("disable")
66 lst
= ["addi 6, 0, 0x10",
71 with
Program(lst
) as program
:
72 self
.run_tst_program(program
, [1])
74 @unittest.skip("disable")
75 def test_example(self
):
76 lst
= ["addi 1, 0, 0x5678",
80 with
Program(lst
) as program
:
81 self
.run_tst_program(program
, [1, 2, 3, 4])
83 @unittest.skip("disable")
85 lst
= ["addi 1, 0, 0x5678",
90 initial_mem
= {0x1230: (0x5432123412345678, 8),
91 0x1238: (0xabcdef0187654321, 8),
93 with
Program(lst
) as program
:
94 self
.run_tst_program(program
,
98 @unittest.skip("disable")
99 def test_ld_rev_ext(self
):
100 lst
= ["addi 1, 0, 0x5678",
105 with
Program(lst
) as program
:
106 self
.run_tst_program(program
, [1, 2, 3])
108 @unittest.skip("disable")
109 def test_st_rev_ext(self
):
110 lst
= ["addi 1, 0, 0x5678",
115 with
Program(lst
) as program
:
116 self
.run_tst_program(program
, [1, 2, 3])
118 @unittest.skip("disable")
119 def test_ldst_extended(self
):
120 lst
= ["addi 1, 0, 0x5678",
125 with
Program(lst
) as program
:
126 self
.run_tst_program(program
, [1, 2, 3])
128 @unittest.skip("disable")
129 def test_0_ldst_widths(self
):
130 lst
= ["addis 1, 0, 0xdead",
140 with
Program(lst
) as program
:
141 self
.run_tst_program(program
, [1, 2, 3, 4, 5])
143 @unittest.skip("disable")
145 lst
= ["addi 1, 0, 0x1234",
148 "subfic 4, 1, 0x1337",
150 with
Program(lst
) as program
:
151 self
.run_tst_program(program
, [1, 2, 3, 4, 5])
153 @unittest.skip("disable")
154 def test_add_with_carry(self
):
155 lst
= ["addi 1, 0, 5",
162 with
Program(lst
) as program
:
163 self
.run_tst_program(program
, [1, 2, 3])
165 @unittest.skip("disable")
166 def test_addis(self
):
167 lst
= ["addi 1, 0, 0x0FFF",
170 with
Program(lst
) as program
:
171 self
.run_tst_program(program
, [1])
173 @unittest.skip("broken")
174 def test_mulli(self
):
175 lst
= ["addi 1, 0, 3",
178 with
Program(lst
) as program
:
179 self
.run_tst_program(program
, [1])
181 def tst_2_load_store(self
):
182 lst
= ["addi 1, 0, 0x1004",
188 initial_regs
= [0] * 32
189 initial_regs
[1] = 0x1004
190 initial_regs
[2] = 0x1008
191 initial_regs
[3] = 0x00ee
192 initial_mem
= {0x1000: (0x5432123412345678, 8),
193 0x1008: (0xabcdef0187654321, 8),
194 0x1020: (0x1828384822324252, 8),
196 with
Program(lst
) as program
:
197 self
.run_tst_program(program
, [3,4], initial_mem
)
199 @unittest.skip("disable")
200 def test_3_load_store(self
):
201 lst
= ["addi 1, 0, 0x1004",
206 initial_regs
= [0] * 32
207 initial_regs
[1] = 0x1004
208 initial_regs
[2] = 0x1002
209 initial_regs
[3] = 0x15eb
210 initial_mem
= {0x1000: (0x5432123412345678, 8),
211 0x1008: (0xabcdef0187654321, 8),
212 0x1020: (0x1828384822324252, 8),
214 with
Program(lst
) as program
:
215 self
.run_tst_program(program
, [1,2,3,4], initial_mem
)
219 register unsigned long i asm ("r12");
227 lst
= ["addi 9, 0, 0x10", # i = 16
228 "addi 9,9,-1", # i = i - 1
229 "cmpi 0,1,9,12", # compare 9 to value 0, store in CR2
230 "bc 4,0,-8" # branch if CR2 "test was != 0"
232 with
Program(lst
) as program
:
233 self
.run_tst_program(program
, [9], initial_mem
={})
235 def run_tst_program(self
, prog
, reglist
, initial_mem
=None):
237 simulator
= self
.run_tst(prog
, initial_mem
=initial_mem
)
239 with
run_program(prog
, initial_mem
) as q
:
240 self
.qemu_register_compare(simulator
, q
, reglist
)
241 self
.qemu_mem_compare(simulator
, q
, reglist
)
242 print(simulator
.gpr
.dump())
244 def qemu_mem_compare(self
, sim
, qemu
, check
=True):
245 if False: # disable convenient large interesting debugging memory dump
247 qmemdump
= qemu
.get_mem(addr
, 2048)
248 for i
in range(len(qmemdump
)):
249 s
= hex(int(qmemdump
[i
]))
250 print ("qemu mem %06x %s" % (addr
+i
*8, s
))
251 for k
, v
in sim
.mem
.mem
.items():
252 qmemdump
= qemu
.get_mem(k
*8, 8)
253 s
= hex(int(qmemdump
[0]))[2:]
254 print ("qemu mem %06x %16s" % (k
*8, s
))
255 for k
, v
in sim
.mem
.mem
.items():
256 print ("sim mem %06x %016x" % (k
*8, v
))
259 for k
, v
in sim
.mem
.mem
.items():
260 qmemdump
= qemu
.get_mem(k
*8, 1)
261 self
.assertEqual(int(qmemdump
[0]), v
)
263 def qemu_register_compare(self
, sim
, qemu
, regs
):
264 qpc
, qxer
, qcr
= qemu
.get_pc(), qemu
.get_xer(), qemu
.get_cr()
265 sim_cr
= sim
.cr
.get_range().value
266 sim_pc
= sim
.pc
.CIA
.value
267 sim_xer
= sim
.spr
['XER'].value
268 print("qemu pc", hex(qpc
))
269 print("qemu cr", hex(qcr
))
270 print("qemu xer", bin(qxer
))
271 print("sim pc", hex(sim
.pc
.CIA
.value
))
272 print("sim cr", hex(sim_cr
))
273 print("sim xer", hex(sim_xer
))
274 self
.assertEqual(qcr
, sim_cr
)
276 qemu_val
= qemu
.get_register(reg
)
277 sim_val
= sim
.gpr(reg
).value
278 self
.assertEqual(qemu_val
, sim_val
)
281 if __name__
== "__main__":