uncomment test_dcache_random
[soc.git] / src / soc / sv / svstate.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4 """SVSATE SPR Record. actually a peer of PC (CIA/NIA) and MSR
5
6 https://libre-soc.org/openpower/sv/sprs/
7
8 | Field | Name | Description |
9 | ----- | -------- | --------------------- |
10 | 0:6 | maxvl | Max Vector Length |
11 | 7:13 | vl | Vector Length |
12 | 14:20 | srcstep | for srcstep = 0..VL-1 |
13 | 21:27 | dststep | for dststep = 0..VL-1 |
14 | 28:29 | subvl | Sub-vector length |
15 | 30:31 | svstep | for svstep = 0..SUBVL-1 |
16 """
17
18 from nmutil.iocontrol import RecordObject
19 from nmigen import Signal
20
21
22 # In nMigen, Record order is from LSB to MSB
23 class SVSTATERec(RecordObject):
24 def __init__(self, name=None):
25 super().__init__(name=name)
26 self.svstep = Signal(2)
27 self.subvl = Signal(2)
28 self.dststep = Signal(7)
29 self.srcstep = Signal(7)
30 self.vl = Signal(7)
31 self.maxvl = Signal(7)