unused_please_ignore_completely/iommu/axi_rab/axi4_r_sender.py

   1 # this file has been generated by sv2nmigen
   2
   3 from nmigen import Signal, Module, Const, Cat, Elaboratable
   4
   5
   6 class axi4_r_sender(Elaboratable):
   7
   8     def __init__(self):
   9         self.axi4_aclk = Signal()  # input
  10         self.axi4_arstn = Signal()  # input
  11         self.drop_i = Signal()  # input
  12         self.drop_len_i = Signal(8)  # input
  13         self.done_o = Signal()  # output
  14         self.id_i = Signal(AXI_ID_WIDTH)  # input
  15         self.prefetch_i = Signal()  # input
  16         self.hit_i = Signal()  # input
  17         self.s_axi4_rid = Signal(AXI_ID_WIDTH)  # output
  18         self.s_axi4_rresp = Signal(2)  # output
  19         self.s_axi4_rdata = Signal(AXI_DATA_WIDTH)  # output
  20         self.s_axi4_rlast = Signal()  # output
  21         self.s_axi4_rvalid = Signal()  # output
  22         self.s_axi4_ruser = Signal(AXI_USER_WIDTH)  # output
  23         self.s_axi4_rready = Signal()  # input
  24         self.m_axi4_rid = Signal(AXI_ID_WIDTH)  # input
  25         self.m_axi4_rresp = Signal(2)  # input
  26         self.m_axi4_rdata = Signal(AXI_DATA_WIDTH)  # input
  27         self.m_axi4_rlast = Signal()  # input
  28         self.m_axi4_rvalid = Signal()  # input
  29         self.m_axi4_ruser = Signal(AXI_USER_WIDTH)  # input
  30         self.m_axi4_rready = Signal()  # output
  31
  32     def elaborate(self, platform=None):
  33         m = Module()
  34         m.d.comb += self.fifo_push.eq(self.None)
  35         m.d.comb += self.done_o.eq(self.fifo_push)
  36         m.d.comb += self.s_axi4_rdata.eq(self.m_axi4_rdata)
  37         m.d.comb += self.s_axi4_ruser.eq(self.None)
  38         m.d.comb += self.s_axi4_rid.eq(self.None)
  39         m.d.comb += self.s_axi4_rresp.eq(self.None)
  40         m.d.comb += self.s_axi4_rvalid.eq(self.None)
  41         m.d.comb += self.m_axi4_rready.eq(self.None)
  42         return m
  43
  44 # // Copyright 2018 ETH Zurich and University of Bologna.
  45 # // Copyright and related rights are licensed under the Solderpad Hardware
  46 # // License, Version 0.51 (the "License"); you may not use this file except in
  47 # // compliance with the License.  You may obtain a copy of the License at
  48 # // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
  49 # // or agreed to in writing, software, hardware and materials distributed under
  50 # // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
  51 # // CONDITIONS OF ANY KIND, either express or implied. See the License for the
  52 # // specific language governing permissions and limitations under the License.
  53 #
  54 # //import CfMath::log2;
  55 #
  56 # module axi4_r_sender
  57 #  #(
  58 #    parameter AXI_DATA_WIDTH = 32,
  59 #    parameter AXI_ID_WIDTH   = 4,
  60 #    parameter AXI_USER_WIDTH = 4
  61 #  )
  62 #  (
  63 #    input  logic                      axi4_aclk,
  64 #    input  logic                      axi4_arstn,
  65 #
  66 #    input  logic                      drop_i,
  67 #    input  logic                [7:0] drop_len_i,
  68 #    output logic                      done_o,
  69 #    input  logic   [AXI_ID_WIDTH-1:0] id_i,
  70 #    input  logic                      prefetch_i,
  71 #    input  logic                      hit_i,
  72 #
  73 #    output logic   [AXI_ID_WIDTH-1:0] s_axi4_rid,
  74 #    output logic                [1:0] s_axi4_rresp,
  75 #    output logic [AXI_DATA_WIDTH-1:0] s_axi4_rdata,
  76 #    output logic                      s_axi4_rlast,
  77 #    output logic                      s_axi4_rvalid,
  78 #    output logic [AXI_USER_WIDTH-1:0] s_axi4_ruser,
  79 #    input  logic                      s_axi4_rready,
  80 #
  81 #    input  logic   [AXI_ID_WIDTH-1:0] m_axi4_rid,
  82 #    input  logic                [1:0] m_axi4_rresp,
  83 #    input  logic [AXI_DATA_WIDTH-1:0] m_axi4_rdata,
  84 #    input  logic                      m_axi4_rlast,
  85 #    input  logic                      m_axi4_rvalid,
  86 #    input  logic [AXI_USER_WIDTH-1:0] m_axi4_ruser,
  87 #    output logic                      m_axi4_rready
  88 #  );
  89 #
  90 #  localparam BUFFER_DEPTH = 16;
  91 #
  92 #  logic                    fifo_valid;
  93 #  logic                    fifo_pop;
  94 #  logic                    fifo_push;
  95 #  logic                    fifo_ready;
  96 #  logic [AXI_ID_WIDTH-1:0] id;
  97 #  logic              [7:0] len;
  98 #  logic                    prefetch;
  99 #  logic                    hit;
 100 #
 101 #  logic                    dropping;
 102 #
 103 #  enum logic [1:0]  { FORWARDING, DROPPING }
 104 #                            state_d,                state_q;
 105 #  logic                     burst_ongoing_d,        burst_ongoing_q;
 106 #  logic [7:0]               drop_cnt_d,             drop_cnt_q;
 107 #
 108 #  axi_buffer_rab
 109 #    #(
 110 #      .DATA_WIDTH       ( 2+AXI_ID_WIDTH+8  ),
 111 #      .BUFFER_DEPTH     ( BUFFER_DEPTH      )
 112 #      )
 113 #    u_fifo
 114 #      (
 115 #        .clk       ( axi4_aclk                              ),
 116 #        .rstn      ( axi4_arstn                             ),
 117 #        // Pop
 118 #        .data_out  ( {prefetch,   hit,   id,   len}         ),
 119 #        .valid_out ( fifo_valid                             ),
 120 #        .ready_in  ( fifo_pop                               ),
 121 #        // Push
 122 #        .valid_in  ( fifo_push                              ),
 123 #        .data_in   ( {prefetch_i, hit_i, id_i, drop_len_i}  ),
 124 #        .ready_out ( fifo_ready                             )
 125 #      );
 126 #
 127 #  assign fifo_push = drop_i & fifo_ready;
 128 #  assign done_o    = fifo_push;
 129 #
 130 #  always_comb begin
 131 #    burst_ongoing_d = burst_ongoing_q;
 132 #    drop_cnt_d      = drop_cnt_q;
 133 #    dropping        = 1'b0;
 134 #    s_axi4_rlast    = 1'b0;
 135 #    fifo_pop        = 1'b0;
 136 #    state_d         = state_q;
 137 #
 138 #    case (state_q)
 139 #      FORWARDING: begin
 140 #        s_axi4_rlast = m_axi4_rlast;
 141 #        // Remember whether there is currently a burst ongoing.
 142 #        if (m_axi4_rvalid && m_axi4_rready) begin
 143 #          if (m_axi4_rlast) begin
 144 #            burst_ongoing_d = 1'b0;
 145 #          end else begin
 146 #            burst_ongoing_d = 1'b1;
 147 #          end
 148 #        end
 149 #        // If there is no burst ongoing and the FIFO has a drop request ready, process it.
 150 #        if (!burst_ongoing_d && fifo_valid) begin
 151 #          drop_cnt_d  = len;
 152 #          state_d     = DROPPING;
 153 #        end
 154 #      end
 155 #
 156 #      DROPPING: begin
 157 #        dropping      = 1'b1;
 158 #        s_axi4_rlast  = (drop_cnt_q == '0);
 159 #        // Handshake on slave interface
 160 #        if (s_axi4_rready) begin
 161 #          drop_cnt_d -= 1;
 162 #          if (drop_cnt_q == '0) begin
 163 #            drop_cnt_d  = '0;
 164 #            fifo_pop    = 1'b1;
 165 #            state_d     = FORWARDING;
 166 #          end
 167 #        end
 168 #      end
 169 #
 170 #      default: begin
 171 #        state_d = FORWARDING;
 172 #      end
 173 #    endcase
 174 #  end
 175 #
 176 #  assign s_axi4_rdata  = m_axi4_rdata;
 177 #
 178 #  assign s_axi4_ruser  = dropping ? {AXI_USER_WIDTH{1'b0}} : m_axi4_ruser;
 179 #  assign s_axi4_rid    = dropping ? id : m_axi4_rid;
 180 #
 181 #  assign s_axi4_rresp  = (dropping & prefetch & hit) ? 2'b00 : // prefetch hit, mutli, prot
 182 #                         (dropping & prefetch      ) ? 2'b10 : // prefetch miss
 183 #                         (dropping            & hit) ? 2'b10 : // non-prefetch multi, prot
 184 #                         (dropping                 ) ? 2'b10 : // non-prefetch miss
 185 #                         m_axi4_rresp;
 186 #
 187 #  assign s_axi4_rvalid =  dropping | m_axi4_rvalid;
 188 #  assign m_axi4_rready = ~dropping & s_axi4_rready;
 189 #
 190 #  always_ff @(posedge axi4_aclk, negedge axi4_arstn) begin
 191 #    if (axi4_arstn == 1'b0) begin
 192 #      burst_ongoing_q <= 1'b0;
 193 #      drop_cnt_q      <=  'b0;
 194 #      state_q         <= FORWARDING;
 195 #    end else begin
 196 #      burst_ongoing_q <= burst_ongoing_d;
 197 #      drop_cnt_q      <= drop_cnt_d;
 198 #      state_q         <= state_d;
 199 #    end
 200 #  end
 201 #
 202 # endmodule
 203 #
 204 #
 205 #
 206 #