reg1_ok = yield dec2.e.read_reg1.ok
if reg1_ok:
data1 = yield dec2.e.read_reg1.data
- res['a'] = sim.gpr(data1).value
+ res['ra'] = sim.gpr(data1).value
# RB
reg2_ok = yield dec2.e.read_reg2.ok
reg3_ok = yield dec2.e.read_reg3.ok
if reg3_ok:
data3 = yield dec2.e.read_reg3.data
- res['rs'] = sim.gpr(data3).value
+ res['rc'] = sim.gpr(data3).value
# XER.ca
carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
# CR (CR0-7)
if cridx_ok:
cr_expected = sim.crl[cridx].get_range().value
- cr_actual = res['cr0']
+ cr_actual = res['cr_a']
print ("CR", cridx, cr_expected, cr_actual)
self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))