rename regspecs to give a consistent naming scheme

[soc.git] / src / soc / fu / compunits / test / test_shiftrot_compunit.py

diff --git a/src/soc/fu/compunits/test/test_shiftrot_compunit.py b/src/soc/fu/compunits/test/test_shiftrot_compunit.py
index 603b3fbbbc85e59a78ea4ff437f266aeefe67844..aeb7de8baf2941db79bff34c5355f49f685c4e3b 100644 (file)
--- a/src/soc/fu/compunits/test/test_shiftrot_compunit.py
+++ b/src/soc/fu/compunits/test/test_shiftrot_compunit.py
@@ -23,7 +23,7 @@ class ShiftRotTestRunner(TestRunner):
         reg1_ok = yield dec2.e.read_reg1.ok
         if reg1_ok:
             data1 = yield dec2.e.read_reg1.data
         reg1_ok = yield dec2.e.read_reg1.ok
         if reg1_ok:
             data1 = yield dec2.e.read_reg1.data

-            res['a'] = sim.gpr(data1).value
+            res['ra'] = sim.gpr(data1).value

 
         # RB
         reg2_ok = yield dec2.e.read_reg2.ok
 
         # RB
         reg2_ok = yield dec2.e.read_reg2.ok


@@ -35,7 +35,7 @@ class ShiftRotTestRunner(TestRunner):
         reg3_ok = yield dec2.e.read_reg3.ok
         if reg3_ok:
             data3 = yield dec2.e.read_reg3.data
         reg3_ok = yield dec2.e.read_reg3.ok
         if reg3_ok:
             data3 = yield dec2.e.read_reg3.data

-            res['rs'] = sim.gpr(data3).value
+            res['rc'] = sim.gpr(data3).value

 
         # XER.ca
         carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
 
         # XER.ca
         carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0


@@ -75,7 +75,7 @@ class ShiftRotTestRunner(TestRunner):
         # CR (CR0-7)
         if cridx_ok:
             cr_expected = sim.crl[cridx].get_range().value
         # CR (CR0-7)
         if cridx_ok:
             cr_expected = sim.crl[cridx].get_range().value

-            cr_actual = res['cr0']
+            cr_actual = res['cr_a']

             print ("CR", cridx, cr_expected, cr_actual)
             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
 
             print ("CR", cridx, cr_expected, cr_actual)
             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))