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Allow the formal engine to perform a same-cycle result in the ALU
[soc.git]
/
src
/
soc
/
decoder
/
isa
/ test_caller_svp64.py
2021-04-23
Luke Kenneth Casso...
removing more as moved over to openpower-isa
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2021-03-24
Luke Kenneth Casso...
make svp64 isa caller unit tests more obvious
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2021-03-21
Luke Kenneth Casso...
naah. back to "sv." syntax for SVP64 assembly
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2021-03-14
Luke Kenneth Casso...
remove "sv." and replace with "sv" in all SVP64Asm
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2021-03-12
Luke Kenneth Casso...
**FOR NOW** LD/ST relies on detection of twin-predicati...
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2021-03-11
Luke Kenneth Casso...
add detection of whether *full* 7-bit of RA is zero...
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2021-03-11
Luke Kenneth Casso...
add in SVP64 LD/ST basic test for ISACaller
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2021-03-03
Luke Kenneth Casso...
remove singleton pattern
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2021-02-27
Luke Kenneth Casso...
add corresponding VL=0 unit test as from 161b7d67b...
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2021-02-21
Luke Kenneth Casso...
create SVP64CROffs consts for when SVP64 Vector-of...
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2021-02-20
Luke Kenneth Casso...
comments on sv.add. Rc=1 unit test
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2021-02-20
Luke Kenneth Casso...
add in Vectorised CRs when Rc=1 into ISACaller
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2021-02-20
Luke Kenneth Casso...
start on CRs in SVP64 mode
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2021-02-15
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-02-13
Luke Kenneth Casso...
update svp64 unit test comments
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2021-02-12
Luke Kenneth Casso...
validate all registers to make sure no damage occurs...
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2021-02-12
Luke Kenneth Casso...
add srcstep and correct PC-advancing during Sub-PC...
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2021-02-12
Luke Kenneth Casso...
add in SVSTATE.srcstep update, loop from 0 to VL-1
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2021-02-12
Luke Kenneth Casso...
fix setting of SVSTATE.VL and MVL
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2021-02-12
Luke Kenneth Casso...
add in SVSTATE to ISACaller, not used, just passed in
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2021-01-31
Luke Kenneth Casso...
start an ISACaller SVP64 unit test
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