Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / decoder / isa / test_caller_svp64.py
2021-04-23 Luke Kenneth Casso... removing more as moved over to openpower-isa
2021-03-24 Luke Kenneth Casso... make svp64 isa caller unit tests more obvious
2021-03-21 Luke Kenneth Casso... naah. back to "sv." syntax for SVP64 assembly
2021-03-14 Luke Kenneth Casso... remove "sv." and replace with "sv" in all SVP64Asm
2021-03-12 Luke Kenneth Casso... **FOR NOW** LD/ST relies on detection of twin-predicati...
2021-03-11 Luke Kenneth Casso... add detection of whether *full* 7-bit of RA is zero...
2021-03-11 Luke Kenneth Casso... add in SVP64 LD/ST basic test for ISACaller
2021-03-03 Luke Kenneth Casso... remove singleton pattern
2021-02-27 Luke Kenneth Casso... add corresponding VL=0 unit test as from 161b7d67b...
2021-02-21 Luke Kenneth Casso... create SVP64CROffs consts for when SVP64 Vector-of...
2021-02-20 Luke Kenneth Casso... comments on sv.add. Rc=1 unit test
2021-02-20 Luke Kenneth Casso... add in Vectorised CRs when Rc=1 into ISACaller
2021-02-20 Luke Kenneth Casso... start on CRs in SVP64 mode
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-13 Luke Kenneth Casso... update svp64 unit test comments
2021-02-12 Luke Kenneth Casso... validate all registers to make sure no damage occurs...
2021-02-12 Luke Kenneth Casso... add srcstep and correct PC-advancing during Sub-PC...
2021-02-12 Luke Kenneth Casso... add in SVSTATE.srcstep update, loop from 0 to VL-1
2021-02-12 Luke Kenneth Casso... fix setting of SVSTATE.VL and MVL
2021-02-12 Luke Kenneth Casso... add in SVSTATE to ISACaller, not used, just passed in
2021-01-31 Luke Kenneth Casso... start an ISACaller SVP64 unit test