first attempt at 3) of
[soc.git] / src / soc / experiment /
2020-10-08 Cole Poirierfirst attempt at 3) of
2020-10-08 Cole Poiriermodify wb_get per 1) of https://bugs.libre-soc.org...
2020-10-07 Tobias Platenconnect mmu_done, ldst_error, cache_paradox
2020-10-06 Tobias Platenremove redunant signals
2020-10-06 Luke Kenneth Casso... update comments on pimem.py
2020-10-06 Tobias Platentest_mmu_dcache_pi.py
2020-10-06 Luke Kenneth Casso... passing LDSTException over to Trap Pipeline
2020-10-06 Luke Kenneth Casso... make LDSTException fields added from list of fieldnames
2020-10-06 Luke Kenneth Casso... move LDSTException to mem_types
2020-10-06 Luke Kenneth Casso... add LDSTException to PortInterface
2020-10-05 Luke Kenneth Casso... add debug / investigation print statements
2020-10-05 Cole Poiriericache.py fix ispow2() util fn per https://bugs.libre...
2020-10-05 Luke Kenneth Casso... whoops fix syntax error
2020-10-05 Luke Kenneth Casso... whoops fix syntax error
2020-10-05 Luke Kenneth Casso... return test rather than "if test return True else False"
2020-10-05 Luke Kenneth Casso... whitespace
2020-10-05 Luke Kenneth Casso... whitespace
2020-10-05 Cole Poiriericache.py add python asserts that were a TODO commented...
2020-10-05 Cole Poiriericache.py fix formatting, mostly due to reduced indenta...
2020-10-05 Cole Poiriericache.py remove comment that contained the entirety...
2020-10-05 Cole Poiriericache.py move icache_miss WAIT_ACK FSM state into...
2020-10-05 Cole Poiriericache.py move icache_miss CLR_TAG FSM state into metho...
2020-10-05 Cole Poiriericache.py move icache_miss IDLE FSM state into method...
2020-10-02 Cole Poiriericache.py add req_hit_way as arg to icache_comb, actual...
2020-10-01 Cole Poiriericache.py add missing comb signal assignments per https...
2020-10-01 Luke Kenneth Casso... arg CacheRam read output needs delay by 1 cycle
2020-10-01 Luke Kenneth Casso... do not pass cache row array around, just the current row
2020-10-01 Luke Kenneth Casso... revert bug in icache wishbone ack
2020-10-01 Cesar StraussAdd GTKWave document to test_compunit_fsm
2020-09-30 Luke Kenneth Casso... clean up row store and wb adr in icache
2020-09-30 Luke Kenneth Casso... hmm only set wishbone address if ack is actually received
2020-09-30 Luke Kenneth Casso... add more debug prints in icache
2020-09-30 Luke Kenneth Casso... remove more reviewed comments
2020-09-30 Luke Kenneth Casso... remove reviewed comments
2020-09-30 Luke Kenneth Casso... comb on wr_index not sync
2020-09-30 Luke Kenneth Casso... start removing reviewed comments
2020-09-30 Luke Kenneth Casso... use same constant name (confusing otherwise)
2020-09-30 Luke Kenneth Casso... need asserts
2020-09-30 Luke Kenneth Casso... halve the number of icache lines for now
2020-09-30 Luke Kenneth Casso... use Repl rather than for-loop to copy bit
2020-09-30 Luke Kenneth Casso... move loop invariant test out of loop
2020-09-30 Luke Kenneth Casso... reduce size of ilang file by a factor of FIVE
2020-09-30 Luke Kenneth Casso... store tag in temp signal
2020-09-30 Luke Kenneth Casso... reduce gate usage by getting cache row only not entire...
2020-09-30 Luke Kenneth Casso... fix read_tag to use word_select correctly
2020-09-30 Luke Kenneth Casso... forgot to add PLRUs as submodules
2020-09-29 Cole Poiriericache.py fix combinatorial loop with by testing temp...
2020-09-29 Cole Poiriericache.py fix is_last_row_addr, get_next_row_addr
2020-09-29 Cole Poiriericache.py trying to sort out test failure, added r...
2020-09-29 Cole Poiriericache.py fix test stbs_done signal, not stbs_zero...
2020-09-29 Cole Poiriericache.py fix rarange
2020-09-29 Cole Poiriericache.py fixed numerous bugs as specified by lkcl...
2020-09-28 Cole Poiriericache.py use d_out as input to assignment instead...
2020-09-27 Cole Poiriericache.py fix translation mistake
2020-09-27 Cesar StraussConvert yet another few tests to be able to use latest...
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-09-25 Cole Poiriericache.py fix several subtle bugs that were lines that...
2020-09-25 Cole Poirierwb_types.py add reset value of 0b11111111 for WBSelType...
2020-09-24 Cole Poiriericache.py add some missing lines from icache.vhdl,...
2020-09-24 Cole Poiriermem_types.py wb_types.py add name constructor to all...
2020-09-24 Cole Poiriericache.py fixed all errors that raised python exception...
2020-09-24 Cesar StraussFix whitespace, remove unused imports
2020-09-24 Luke Kenneth Casso... brackets round imports looks cleaner?
2020-09-24 Cesar StraussUse nmutil simulator module to simplify choosing among...
2020-09-22 Cesar StraussPort soc.experiment.alu_fsm to the new way of invoking...
2020-09-20 Cesar StraussAdd induction proof for the FSM Shifter
2020-09-20 Cesar StraussAdd bounded proof to FSM Shifter
2020-09-20 Cesar StraussLet the formal engine create some test cases for the...
2020-09-20 Luke Kenneth Casso... resolve issues in async sim: must not drive async clock...
2020-09-20 Luke Kenneth Casso... still experimenting with async FF sync
2020-09-20 Luke Kenneth Casso... continuing async clock experimenting
2020-09-20 Luke Kenneth Casso... add an async clock synchronizer experiment
2020-09-20 Luke Kenneth Casso... first version code-morph on dmi2jtag
2020-09-19 Cesar StraussRemove demonstration code
2020-09-16 Cole Poiriercomplete first translation pass of dmi_dtm_xilinx.vhdl...
2020-09-16 Cole Poirierinitial commit of JTAGToDMI debug interface translated...
2020-09-15 Luke Kenneth Casso... comment mmu test
2020-09-15 Luke Kenneth Casso... add set MTSPR prtbl to mmu unit test
2020-09-15 Luke Kenneth Casso... add extra "modes" to PortInterface
2020-09-15 Luke Kenneth Casso... syntax error correction
2020-09-15 Luke Kenneth Casso... add inline comments into icache.py
2020-09-14 Cole Poiriericache.py add missing funciton bodies, add missing...
2020-09-14 Luke Kenneth Casso... increase TLB_NUM_WAYS to 4
2020-09-14 Luke Kenneth Casso... vhdl conversion not really working for plru
2020-09-14 Luke Kenneth Casso... add array signal names
2020-09-14 Luke Kenneth Casso... rename plru input
2020-09-14 Luke Kenneth Casso... rename plru input
2020-09-14 Luke Kenneth Casso... reorg mmu lookup test so it is called twice
2020-09-14 Luke Kenneth Casso... TLB PLRUs are of TLB_WAY_BITS width
2020-09-14 Luke Kenneth Casso... fix mmu perms/lookup in dcache
2020-09-14 Luke Kenneth Casso... whitespace
2020-09-14 Luke Kenneth Casso... remove duplicated signal
2020-09-14 Luke Kenneth Casso... comments on icache
2020-09-14 Luke Kenneth Casso... get rid of rst
2020-09-14 Luke Kenneth Casso... use word_select
2020-09-14 Luke Kenneth Casso... add mmu-dcache test
2020-09-14 Cole Poiriericache.py connect up all the sub-functions, fix typos...
2020-09-14 Cole Poiriericache.py add parameters to 'process' functions, fix...
2020-09-13 Cole Poiriericache.py move get/read/write functions out of ICache...
2020-09-13 Cole Poiriericache.py copy simulation code from dcache.py, fix...
next