radix: reading first page table entry
[soc.git] / src / soc / fu /
2021-03-09 Cesar StraussEnable VL==0 vector instruction skip test case
2021-03-08 Luke Kenneth Casso... correct comments in sv.add rc=1
2021-03-07 Luke Kenneth Casso... add Rc=1 SVP64 unit test to svp64_cases.py
2021-03-06 Cesar StraussEnable the Simple-V loop test case
2021-03-02 Luke Kenneth Casso... comment out changing SPR 720 because 720 is not support...
2021-03-02 Luke Kenneth Casso... sort out SPR setting in MMU
2021-03-02 Luke Kenneth Casso... operating correctly, not directing MMU SPRs to SPR...
2021-03-02 Luke Kenneth Casso... must always set ok for writing out data otherwise it...
2021-02-26 Cesar StraussAdd a vector case with VL == 0
2021-02-24 Tobias Platenupdate mmu testcase
2021-02-20 Luke Kenneth Casso... correct arguments, set microwatt_mmu=True, pass in...
2021-02-20 Luke Kenneth Casso... minor whitespace cleanup
2021-02-20 Tobias Platenmmu testcase: set MMU SPRs
2021-02-20 Tobias Platenadd rom debugger
2021-02-20 Tobias Platenadd mmu rom testcase
2021-02-18 Tobias Platenmmu: remove TestMemory
2021-02-17 Cesar StraussAdd a case for checking the EXTRA field and register...
2021-02-16 Tobias Platenmmureq handling
2021-02-16 Tobias Platendcache error handling
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-15 Tobias Platentest case for MMU SPRs: PID and PRTBL
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-13 Cesar StraussSkip vector test case, and add a scalar case
2021-02-13 Cesar StraussFix imports and whitespace
2021-02-13 Luke Kenneth Casso... add SVP64 TestIssuer separate unit test
2021-02-12 Luke Kenneth Casso... add one SVP64 ALU test case to get started
2021-02-12 Luke Kenneth Casso... add SVSTATE to TestCase infrastructure for use in TestI...
2021-02-05 Tobias Platenfix hanging simulation
2021-02-04 Tobias Platensrc/soc/fu/mmu/fsm.py: add debug outputs for gtkwave
2021-02-04 Tobias Platenupdate test_issuer_mmu_data_path.py to handle SPRs
2021-01-31 Luke Kenneth Casso... adjusting ISACaller unit test to use ISACaller.setup_one()
2021-01-29 Luke Kenneth Casso... whoops missed out "+" on explicit license listing
2021-01-19 Tobias Platentest_issuer_mmu_data_path.py: test both ld and st instr...
2021-01-19 Tobias Platenconnect LDSTException to MMU and DCache
2021-01-19 Tobias Platenconnect wishbone bus to test memory
2021-01-18 Tobias Platenfu/mmu/fsm.py: connect valid and load signals
2021-01-17 Tobias Platenadd test memory for simulation
2021-01-17 Tobias Platencleanup test_issuer_mmu_data_path.py
2021-01-16 Tobias Platenclean up test case for tlbie and dcbz
2021-01-16 Tobias Platenmove microwatt_mmu bool variable to pspec
2021-01-16 Tobias Platenadd new unittest: test_issuer_mmu_data_path.py
2021-01-15 Tobias Platencleanup test_non_production_core.py
2021-01-15 Tobias Platenadd microwatt_mmu boolean variable to core and compunits
2021-01-15 Tobias Platentest_non_production_core.py: fix hanging test
2021-01-15 Tobias Platentest_non_production_core.py: wire instruction decoder...
2021-01-14 Tobias Platenadd test case for mmu+NonProductionCore
2021-01-10 Tobias Platenadd microwatt mmu config option to compunits.py
2021-01-07 Tobias Platenset initial_sprs, cleanup mfspr testprog
2021-01-07 Tobias Platenmfspr is RT, SPR
2021-01-06 Tobias Platenfirst testcase for mmu: case_mfspr_after_invalid_load
2021-01-06 Tobias Platenfu/mmu/fsm.py: mfspr!=mtspr
2021-01-04 Tobias Platentest_countzero.py: rename output files
2020-12-13 Cesar StraussIgnore formal verification output in the source directory
2020-12-12 Luke Kenneth Casso... skip madd, not implemented
2020-12-06 Cesar StraussWhitespace
2020-12-06 Cesar StraussUpdate GTKWave documents to work with latest cxxsim
2020-12-05 Cesar StraussWrite a GTKWave document to investigate why the proof...
2020-12-05 Cesar StraussUse the DummyALU regspec and its corresponding OpSubset
2020-11-28 Cesar StraussFix signal names: go/rel -> go_i/rel_o
2020-11-17 Tobias Platentestcase for dcbz
2020-11-16 Tobias Platenadd class LoadStore1(PortInterfaceBase)
2020-11-11 Tobias Platendcbz and tlbie first test, still incomplete
2020-11-11 Tobias Platenfu/mmu/test/test_pipe_caller.py test case for mfspr
2020-11-08 Tobias Platenmmu fsm testcase: add check_fsm_outputs based on functi...
2020-11-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-11-08 Tobias Platenmmu/fsm: test case for mtspr
2020-11-07 Tobias Platenfixed a bug in src/soc/fu/mmu/fsm.py
2020-11-04 Tobias PlatenMMU: begin test case for 'dcbz'
2020-11-03 Tobias Platenfix broken unittest after installing power-instruction...
2020-10-20 Tobias Platens/alu/fsm/g
2020-10-20 Tobias Platentest case for FSMMMUStage
2020-10-16 Luke Kenneth Casso... experiment swapping dummy trap stage over to input
2020-10-16 Luke Kenneth Casso... add extra (test dummy stage in trap to see if combinato...
2020-10-16 Luke Kenneth Casso... add LGPLv3+ notice and add copyright holders
2020-10-12 Cole Poirierfix ModuleNotFound/Import errors found when running...
2020-10-09 Jacob Lifshayfinish converting mul tests to use common code
2020-10-09 Jacob Lifshayworking on splitting out common mul pipe test code
2020-10-09 Jacob Lifshayadd carry handling to pia_res_to_output
2020-10-09 Jacob Lifshaymove pia_res_to_output to common test helpers
2020-10-09 Jacob Lifshaymove mul pipe ilang test to separate file
2020-10-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-10-08 Tobias Platenadd WIP test_pipe_caller.py for mmu
2020-10-08 Luke Kenneth Casso... add incoming PortInterface to be connected to LoadStore...
2020-10-07 Luke Kenneth Casso... missing invert_in field from shiftrot input record
2020-10-07 Jacob Lifshayfix div tests
2020-10-07 Jacob LifshayFix forgotten test_pipe_caller changes from e0b4334c7d8...
2020-10-06 Luke Kenneth Casso... use pdecode2.do not pdecode2.e in test_pipe_caller...
2020-10-06 Luke Kenneth Casso... skip Decode2ToOperand from PowerDecodeSubset
2020-10-06 Luke Kenneth Casso... add SRR1 setting for LDST memory exception trap
2020-10-06 Luke Kenneth Casso... passing LDSTException over to Trap Pipeline
2020-10-06 Luke Kenneth Casso... add LDSTException decode/handling in PowerDecoder2
2020-10-06 Jacob Lifshayadd divde regression test
2020-10-06 Jacob Lifshayadd moduw regression test
2020-10-06 Jacob Lifshayadd workaround for nmigen bug #502
2020-10-06 Jacob Lifshayadd modsw regression
2020-10-06 Jacob Lifshayadd test case for divweu regression
2020-10-06 Jacob Lifshayprint regs in hex
2020-10-04 Jacob Lifshaychange div FSM pipeline unit to not have a combinatoria...
2020-10-03 Jacob Lifshayadd regression testcase
2020-09-27 Cesar StraussConvert yet another few tests to be able to use latest...