git.libre-soc.org Git - soc.git/history - src/soc/simple/test/teststate.py

[soc.git] / src / soc / simple / test / teststate.py

2021-09-21	Luke Kenneth Casso...	convert HDLState.get_mem() to a dictionary of memory...	blob \| commitdiff \| raw
2021-09-20	Luke Kenneth Casso...	use get_l0_mem in HDLState to get memory data	blob \| commitdiff \| raw \| diff to current
2021-09-18	Luke Kenneth Casso...	always store full memory state (including zeros)	blob \| commitdiff \| raw \| diff to current
2021-09-18	klehman	added get_mem	blob \| commitdiff \| raw \| diff to current
2021-09-15	isengaara	Merge branch 'master' of ssh://git.libre-riscv.org...	blob \| commitdiff \| raw \| diff to current
2021-09-14	Luke Kenneth Casso...	convert to using TestState and State after moving to...	blob \| commitdiff \| raw \| diff to current
2021-09-14	klehman	factory add and intro doc string	blob \| commitdiff \| raw \| diff to current
2021-09-12	Luke Kenneth Casso...	use log instead of print	blob \| commitdiff \| raw \| diff to current
2021-09-12	Luke Kenneth Casso...	create new function teststate_check_regs which is calle...	blob \| commitdiff \| raw \| diff to current
2021-09-12	klehman	added compare function	blob \| commitdiff \| raw \| diff to current
2021-09-12	klehman	added factory function for test class creation	blob \| commitdiff \| raw \| diff to current
2021-09-10	klehman	implement base class in state class	blob \| commitdiff \| raw \| diff to current
2021-09-09	klehman	made sim into generators and some uniformity changes	blob \| commitdiff \| raw \| diff to current
2021-09-09	klehman	finished remaining hdl items	blob \| commitdiff \| raw \| diff to current
2021-09-09	klehman	HDL int reg added	blob \| commitdiff \| raw \| diff to current
2021-09-09	klehman	more sim class registers add	blob \| commitdiff \| raw \| diff to current
2021-09-08	klehman	initial commit of sim state class	blob \| commitdiff \| raw \| diff to current

RSS Atom