| 2020-08-14 |
Luke Kenneth Casson... | move instruction decoder out of core
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commit | commitdiff | tree |
| 2020-08-14 |
Luke Kenneth Casson... | move regspec / rdflag decoding functions out of PowerDecode2
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commit | commitdiff | tree |
| 2020-08-14 |
Luke Kenneth Casson... | sort out instruction stop/cancel when adding a new...
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commit | commitdiff | tree |
| 2020-08-14 |
Luke Kenneth Casson... | put multi-ports back (for read) on int and fast regfiles
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commit | commitdiff | tree |
| 2020-08-14 |
Luke Kenneth Casson... | reduce decoder pathways when exception occurs
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commit | commitdiff | tree |
| 2020-08-14 |
Luke Kenneth Casson... | divide shiftrot pipeline into 2 (simple last)
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commit | commitdiff | tree |
| 2020-08-14 |
Luke Kenneth Casson... | divide alu pipeline into 2 (simple last)
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commit | commitdiff | tree |
| 2020-08-14 |
Luke Kenneth Casson... | divide logical pipe into 2 (simple phase last)
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | fix dmi reg read
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | code-shuffle
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | remove use of latchregigister, replace with sync on...
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | sync on pc writing when changed
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | sync on reset in compalu
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | add forwarding-bus mode to Regfile Memory (and disable it)
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | sync on port interface address in ld/st compunit, and...
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | another sync to cut latency
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | remove latchregister, sync src oper_i into MultiCompUnit
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | minor tidyup on alu compunit:
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | plenty of time to wait for operand, so use "sync" in...
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | sigh. convert Fast regfile to binary
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | sync on read of regfile ports
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | sigh. convert INT regfile to binary addressing
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commit | commitdiff | tree |
| 2020-08-13 |
Luke Kenneth Casson... | create a RegFileMem class that uses Memory
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commit | commitdiff | tree |
| 2020-08-11 |
Luke Kenneth Casson... | sigh, remove yet another int regfile read port
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commit | commitdiff | tree |
| 2020-08-11 |
Luke Kenneth Casson... | massive reduction in gate count by using alternative...
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commit | commitdiff | tree |
| 2020-08-11 |
Luke Kenneth Casson... | reduce regfile port usage for INT and FAST
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commit | commitdiff | tree |
| 2020-08-11 |
Luke Kenneth Casson... | prepare write ports to be shared
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commit | commitdiff | tree |
| 2020-08-11 |
Luke Kenneth Casson... | move write regfile picker creation to new function
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commit | commitdiff | tree |
| 2020-08-11 |
Luke Kenneth Casson... | reduce regfile ports by creating separate STATE regfile
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commit | commitdiff | tree |
| 2020-08-11 |
Luke Kenneth Casson... | whoops fix change of variable (state) msr/pc
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commit | commitdiff | tree |
| 2020-08-11 |
Luke Kenneth Casson... | reducing regfile port usage by sharing read ports
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commit | commitdiff | tree |
| 2020-08-09 |
Luke Kenneth Casson... | stop combinatorial loop in pi2ls
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commit | commitdiff | tree |
| 2020-08-09 |
Luke Kenneth Casson... | write pulse in issuer
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commit | commitdiff | tree |
| 2020-08-09 |
Luke Kenneth Casson... | fix combinatorial loop in ldst compunit
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commit | commitdiff | tree |
| 2020-08-09 |
Luke Kenneth Casson... | use rising edge detection on st go_i/rel_o
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commit | commitdiff | tree |
| 2020-08-09 |
Luke Kenneth Casson... | add logical test issuer case
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commit | commitdiff | tree |
| 2020-08-09 |
Luke Kenneth Casson... | get rid of MSR read combinatorial loop
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commit | commitdiff | tree |
| 2020-08-09 |
Luke Kenneth Casson... | delay go_st by one cycle, break combinatorial loop
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commit | commitdiff | tree |
| 2020-08-09 |
Luke Kenneth Casson... | divwo case makes test_issuer stay busy!
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commit | commitdiff | tree |
| 2020-08-09 |
Luke Kenneth Casson... | add extra divwo regression test
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commit | commitdiff | tree |
| 2020-08-09 |
Luke Kenneth Casson... | compalu combinatorial loop detected
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commit | commitdiff | tree |
| 2020-08-06 |
Luke Kenneth Casson... | fix LDST PortInterface FSM interaction
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commit | commitdiff | tree |
| 2020-08-06 |
Luke Kenneth Casson... | MULS on parameter b needed to check whether it was...
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commit | commitdiff | tree |
| 2020-08-05 |
Luke Kenneth Casson... | rename ibus/dbus (shorten)
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commit | commitdiff | tree |
| 2020-08-05 |
Luke Kenneth Casson... | clear sel on loadstore
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commit | commitdiff | tree |
| 2020-08-05 |
Luke Kenneth Casson... | adding bus data width of 64 in litex sim doesnt work
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commit | commitdiff | tree |
| 2020-08-05 |
Luke Kenneth Casson... | add div test cases into test_issuer.py
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commit | commitdiff | tree |
| 2020-08-05 |
Luke Kenneth Casson... | add div FSM as default for test_issuer in verilog and...
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | read/set pc outside of FSM so that DMI interface can...
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | swap over byte-reverse if/else in LDSTCompUnit
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | tracked down byte-reversal in LDST ISACaller and LDSTCompUnit
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | whitespace after autopep8 messed up
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | msr and pc moved to "state" in PowerDecode2
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | whoops must output NIA not PC to debug DMI query in...
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | allow instruction to run if initiated whilst "stopped...
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | cycle through INT regs, read and debug in litex sim
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | add DMI debug interface to libresoc litex sim
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | single-step and print out PC using DMI in litex sim
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | get litex sim to kick off a "STEP" via the DMI interface...
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | connect up a DMI FSM to litex sim
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | more remove wildcard imports
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | do not use wildcard imports
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commit | commitdiff | tree |
| 2020-08-04 |
Luke Kenneth Casson... | adding litex sim experimentation.
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commit | commitdiff | tree |
| 2020-08-03 |
Luke Kenneth Casson... | add quick demo/test of reading DMI reg 9
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commit | commitdiff | tree |
| 2020-08-03 |
Luke Kenneth Casson... | add extra port for debug read of int regs via DMI
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commit | commitdiff | tree |
| 2020-08-03 |
Luke Kenneth Casson... | pass state (MSR/PC) around between PowerDecode2, DMI...
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commit | commitdiff | tree |
| 2020-08-03 |
Luke Kenneth Casson... | https://bugs.libre-soc.org/show_bug.cgi?id=446
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commit | commitdiff | tree |
| 2020-08-03 |
Luke Kenneth Casson... | use new soc.config.state CoreState class in DMI and...
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commit | commitdiff | tree |
| 2020-08-03 |
Luke Kenneth Casson... | change over to DMI debug start/stop interface
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commit | commitdiff | tree |
| 2020-08-03 |
Luke Kenneth Casson... | move debug to record
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commit | commitdiff | tree |
| 2020-08-02 |
Luke Kenneth Casson... | convert microwatt core_debug.vhdl to nmigen
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commit | commitdiff | tree |
| 2020-08-02 |
Luke Kenneth Casson... | add debug dir
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commit | commitdiff | tree |
| 2020-08-01 |
Luke Kenneth Casson... | add quick test of litex bios IMM64 macro
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commit | commitdiff | tree |
| 2020-08-01 |
Luke Kenneth Casson... | add rlwnm test showing that shift rot OP_RLC proof...
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commit | commitdiff | tree |
| 2020-08-01 |
Luke Kenneth Casson... | line-length / whitespace
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commit | commitdiff | tree |
| 2020-08-01 |
Luke Kenneth Casson... | expand out for-loop setting up input record subset
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commit | commitdiff | tree |
| 2020-07-31 |
Luke Kenneth Casson... | reorg DecodeB in power_decoder2.py to sign-extend immediates
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commit | commitdiff | tree |
| 2020-07-31 |
Luke Kenneth Casson... | add more instructions to litex trampoline test (not...
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commit | commitdiff | tree |
| 2020-07-31 |
Luke Kenneth Casson... | restrict external port list further in test_issuer
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commit | commitdiff | tree |
| 2020-07-31 |
Luke Kenneth Casson... | missed go_i/rel_o rename
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commit | commitdiff | tree |
| 2020-07-30 |
Luke Kenneth Casson... | core_start/stop/endian were inverted (output)
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commit | commitdiff | tree |
| 2020-07-30 |
Luke Kenneth Casson... | ha! have to explicitly specify the ports when writing...
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commit | commitdiff | tree |
| 2020-07-30 |
Luke Kenneth Casson... | add trampoline test from litex
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commit | commitdiff | tree |
| 2020-07-30 |
Luke Kenneth Casson... | set sel line in minerva instruction fetch
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commit | commitdiff | tree |
| 2020-07-30 |
Luke Kenneth Casson... | ha! found source of XICS test bug: wishbone stb was...
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commit | commitdiff | tree |
| 2020-07-29 |
Luke Kenneth Casson... | more exploratory testing of XICS, joining ICP and ICS...
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commit | commitdiff | tree |
| 2020-07-29 |
Luke Kenneth Casson... | forgot to rename ad/st in LDSTCompUnitRecord
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commit | commitdiff | tree |
| 2020-07-29 |
Luke Kenneth Casson... | bit of a big change: add prefixes "cu_" to all CompUnit...
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commit | commitdiff | tree |
| 2020-07-29 |
Luke Kenneth Casson... | start on test joining XICS ICS to ICP
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commit | commitdiff | tree |
| 2020-07-29 |
Luke Kenneth Casson... | tidyup XICS, identify (potential?) bug?
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commit | commitdiff | tree |
| 2020-07-29 |
Luke Kenneth Casson... | move CR test out of subtest indentation
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commit | commitdiff | tree |
| 2020-07-29 |
Luke Kenneth Casson... | move SHIFTROT test out of subtest indentation
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commit | commitdiff | tree |
| 2020-07-29 |
Luke Kenneth Casson... | move actual ALU test out of subTest indentation just...
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commit | commitdiff | tree |
| 2020-07-29 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
| 2020-07-28 |
Luke Kenneth Casson... | use ctx.op compare (and muxid) in shiftrot proof
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commit | commitdiff | tree |
| 2020-07-28 |
Luke Kenneth Casson... | add preliminary investigative test of XICS ICS
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commit | commitdiff | tree |
| 2020-07-28 |
Luke Kenneth Casson... | tidyup/comments in trap proof
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commit | commitdiff | tree |
| 2020-07-27 |
Luke Kenneth Casson... | add 2nd part of XICS interrupt interface
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commit | commitdiff | tree |
| 2020-07-27 |
Luke Kenneth Casson... | fix trap proof, and trap main_stage, and pseudocode...
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commit | commitdiff | tree |
| 2020-07-27 |
Luke Kenneth Casson... | shorten expected_ to exp_, gets line-length down
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commit | commitdiff | tree |
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