soc.git
10 hours ago Luke Kenneth... submodule update master
10 hours ago Luke Kenneth... whitespace
10 hours ago Luke Kenneth... submodule update
10 hours ago Tobias Platenupdate test_caller_radix.py
11 hours ago Tobias Platenradixmmu: handle badtree
11 hours ago Tobias Platenupdate test case for radix mmu
11 hours ago Tobias Platenradixmmu: error handling
35 hours ago Tobias Platenmore fixes for radixmmu.py
36 hours ago Tobias Platenfix AttributeError in radixmmu testcase
2 days ago Tobias Platenradixmmu.py: cleanup
3 days ago Tobias Platenfix bug in radixmmu.py
3 days ago Tobias Platenradixmmu: more work on segment check
4 days ago Cesar StraussImplement 1<<r3 predicate mode
4 days ago Cesar StraussAdd 1<<r3 test cases to TestIssuer
4 days ago Cesar StraussAdd test cases for 1<<r3 predication
5 days ago Luke Kenneth... add blinken lights assembly (not used yet)
6 days ago Luke Kenneth... test firmware upload program needed to branch back...
6 days ago Luke Kenneth... sort out pc reset when DMI interface requests reset
6 days ago Luke Kenneth... submodule update
6 days ago Luke Kenneth... argh, wb jtag stall probably is not working
6 days ago Luke Kenneth... upload over 32-bit JTAG Wishbone
6 days ago Luke Kenneth... shrink JTAG master bus to 32-bit (match with litex)
7 days ago Luke Kenneth... submodule update
7 days ago Tobias PlatenWIP: calculate address of first page table entry
7 days ago Tobias Platenradixmmu: fix segment_check function and its caller
8 days ago Luke Kenneth... 4k SRAM Instance needs write-enable @ 8-bit width
8 days ago Luke Kenneth... 8-bit granularity on JTAG wishbone
8 days ago Luke Kenneth... remove unneeded code
8 days ago Staf Verhaegensoc-cocotb-sim submodule update
8 days ago Tobias Platenadd mmu_states.dia
8 days ago Luke Kenneth... git submodule update
8 days ago Cesar StraussMake the VL loop reentrant in HDL
8 days ago Cesar StraussAdd a HDL test case, where we start at the middle of...
8 days ago Cesar StraussStart the test case from a point where the predicate...
9 days ago Luke Kenneth... litex submodule update
9 days ago Luke Kenneth... submodule update
10 days ago Staf Verhaegensoc-cocotb-sim submodule update
10 days ago Cesar StraussAdd test case for reentrant VL loop
11 days ago Cesar StraussReminder for a possible hardware optimization
11 days ago Cesar StraussBe more precise when using a one-bit constant
11 days ago Cesar StraussFix typo
11 days ago Cesar StraussAdd test case with all mask bits equal to zero
11 days ago Cesar StraussAdd a test case for integer single predication
11 days ago Cesar StraussDisallow unknown encmodes in SVP64 Assembly
11 days ago Cesar StraussEnable remaining disabled test cases
11 days ago Cesar StraussAllow the Simulator to handle back-to-back signaling...
11 days ago Cesar StraussSignal the simulator when completing a VL loop
11 days ago Cesar StraussFix typo
11 days ago Cesar StraussAdd twin predication test
12 days ago Cesar StraussEnd VL loop as soon as either src/dst step reaches VL
12 days ago Cesar StraussFix typo
12 days ago Cesar StraussAdd VEXPAND test case for the ISA Simulator
12 days ago Cesar StraussAdd VCOMPRESS test case for the ISA Simulator
12 days ago Cesar StraussPut sanity check inside the existing '2Pred' case,...
12 days ago Cesar StraussEnforce explicit src/dest masks on CR twin-predication
12 days ago Cesar StraussDisallow mixing of sm=xx and/or dm=xx with m=xx on...
12 days ago Cesar StraussDisallow dm=xx on single predication
12 days ago Cesar StraussFix typo
12 days ago Cesar StraussReally enforce sm=xx not being allowed on single-pred
12 days ago Cesar StraussKeep mask mode flags separate
13 days ago Luke Kenneth... git submodule update
13 days ago Luke Kenneth... TWI enabled in JTAG boundary scan
13 days ago Luke Kenneth... git submodule update
13 days ago Luke Kenneth... reduce subset of functions to be created in JTAG bounda...
13 days ago Luke Kenneth... use OrderedDict to restore exact order from JSON file
13 days ago Luke Kenneth... add soc-cocotb-sim submodule
13 days ago Luke Kenneth... submodule update
13 days ago Staf Verhaegenlibresoc-litex submodule update
13 days ago Luke Kenneth... bug in iverilog, segfaults due to empty case statement
13 days ago Luke Kenneth... add no pll ls180 build
13 days ago Staf Verhaegenlibresoc-litex submodule update
2021-03-31 Tobias Platen_new_lookup: remove unused argument mbits
2021-03-31 Tobias Platenradixmmu: read prtable entry
2021-03-31 Tobias Platenradixmmu.py: remove redunant code
2021-03-31 Luke Kenneth... submodule update
2021-03-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-03-30 Tobias Platenmore work on _prtable_lookup and testcase
2021-03-30 Luke Kenneth... add comments
2021-03-30 Luke Kenneth... use PRTBL SPR in RADIXMMU
2021-03-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-03-30 Tobias Platencomment about microwatt implementation details
2021-03-30 Luke Kenneth... submodule update
2021-03-30 Luke Kenneth... add comments, correct load addresses
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-30 Alain D D WilliamsAllow comments
2021-03-30 Tobias Platenadd function _prtable_lookup and unit test
2021-03-30 Luke Kenneth... submodule update
2021-03-30 Luke Kenneth... might have RADIXMMU at least semi-working... maybe
2021-03-30 Luke Kenneth... use assertEqual in RADIXMMU unit test
2021-03-30 Luke Kenneth... skip 1-pred check if m= used in SVP64Asm
2021-03-30 Cesar StraussEnable VCOMPRESS test case
2021-03-30 Luke Kenneth... submodule update
2021-03-30 Cesar StraussAdd new twin predication case
2021-03-30 Cesar StraussAdjust twin predication cases for the new syntax
2021-03-30 Cesar StraussSkip leading zero bits on predicate masks
2021-03-30 Luke Kenneth... use port name for INT regfile to match up with test_run...
2021-03-30 Luke Kenneth... corrections to Makefile for building / not-building...
2021-03-30 Cesar StraussMemory port seems to have been renamed
2021-03-30 Luke Kenneth... bit of munging of Makefile, new targets
2021-03-30 Luke Kenneth... whoops Makefile error
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