argh, found the blackbox problem: yosys is "doing the right thing" and
[soclayout.git] / examples /
2020-02-22 Luke Kenneth Casso... move Makefile3/4 to experiments3
2020-02-22 Luke Kenneth Casso... move part_sig_add to its own directory
2020-02-22 Luke Kenneth Casso... move alu_hier to own directory
2020-02-21 Luke Kenneth Casso... reduce pmask to stop unconnected bits
2020-02-21 Luke Kenneth Casso... use alternative experimental class TestAddMod2
2020-02-20 Luke Kenneth Casso... fix mask width
2020-02-20 Luke Kenneth Casso... add Makefile3
2020-02-20 Luke Kenneth Casso... add second Makefile
2020-02-20 Luke Kenneth Casso... move part_sig_add name
2020-02-20 Luke Kenneth Casso... remove clock
2020-02-19 Luke Kenneth Casso... remove clock, use rename on clk in settings
2020-02-19 Luke Kenneth Casso... add clocks and reset and add alu.py as well
2020-02-19 Luke Kenneth Casso... add alu_hier.py example
2020-02-14 Tobias Platenfirst example code