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include (but do not use) FreePDK45 in experiments10
[soclayout.git]
/
experiments10_verilog
/
2021-04-12
Luke Kenneth Casso...
include (but do not use) FreePDK45 in experiments10
tree
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commitdiff
2021-04-12
Luke Kenneth Casso...
different FreePDK45 experiments10 chip size
tree
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commitdiff
2021-04-12
Luke Kenneth Casso...
experimentation to get experiment10_verilog work with...
tree
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commitdiff
2021-04-12
Luke Kenneth Casso...
add FreePDK45 experiments10_verilog doDesign.py
tree
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commitdiff
2021-04-12
Luke Kenneth Casso...
add FreePDK45 variant of experiments10_verilog
tree
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commitdiff
2021-04-12
Luke Kenneth Casso...
rename sys_clk in adder test experiments10_verilog...
tree
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commitdiff
2021-04-12
Luke Kenneth Casso...
rename JTAG port in adder test experiments10_verilog...
tree
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commitdiff
2021-04-12
Luke Kenneth Casso...
back to "working" verilog add
tree
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commitdiff
2021-04-09
Luke Kenneth Casso...
sigh, broken experiment10_verilog
tree
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commitdiff
2021-04-09
Luke Kenneth Casso...
whitespace cleanup
tree
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commitdiff
2021-04-09
Luke Kenneth Casso...
pad name starts with p_
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commitdiff
2021-04-09
Luke Kenneth Casso...
rename design of experiments10 to match ls180 chip...
tree
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commitdiff
2021-04-02
Luke Kenneth Casso...
experiment with nmigen verilog generation
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commitdiff